Víctor H. Champac

96 papers A 2B 5C 8Misc 11Journal 37Unranked 33

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Novel Defect Model Induced by a Single Dust Particle Contamination in the FinFET Gate Fingers. J. Electron. Test. Gustavo Aguirre, Víctor H. Champac, Freddy Forero, Michel Renovell, Leonardo Miceli
2025	J	`jnl`	Cost-Effective Analytical Models of Resistive Opens Defects in FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. Gustavo Aguirre, Freddy Forero, Víctor H. Champac, Michel Renovell, Florence Azaïs, Mariane Comte, Jean-Marc Gallière
2025	—	`conf`	Design and Functional Simulation of a Specialized EEPROM for Reliable Storage of Physiological Data in FPGA Environments Using Xilinx ISE. ENC Jazmín Stephanie Hernández Martínez, Zaid Segundo Hernández Martínez, Daemon Vera, Víctor H. Champac, Pedro Mabil-Espinosa, Jaime Martínez-Castillo
2025	—	`conf`	Investigating Manufacturing Defects Leading to Potential Silent Data Errors. LATS Jorge Lopez, Víctor H. Champac
2024	J	`jnl`	Failure Probability due to Radiation-Induced Effects in FinFET SRAM Cells under Process Variations. J. Electron. Test. Víctor H. Champac, Hector Villacorta, Roberto Gómez-Fuentes, Fabian Vargas, Jaume Segura
2024	—	`conf`	Fault Analysis for a MTJ-based Spiking Neural Network. LATS Leonardo Miceli, Elena-Ioana Vatajelu, Víctor H. Champac
2023	—	`conf`	A New Defect Model due to a Dust Particle Affecting the Fingers of FinFET Logic Gates. LATS Víctor H. Champac, Freddy Forero, Michel Renovell, Leonardo Miceli
2023	J	`jnl`	B-open Defect: A Novel Defect Model in FinFET Technology. ACM J. Emerg. Technol. Comput. Syst. Freddy Forero, Víctor H. Champac, Michel Renovell
2022	—	`conf`	Failure Probability due to Radiation-induced Effects in FinFET SRAM Cells under Process Variations. LATS Víctor H. Champac, Hector Villacorta, Roberto Gómez-Fuentes, Fabian Vargas, Jaume Segura
2021	J	`jnl`	Analysis and Detection of Open-gate Defects in Redundant Structures of a FinFET SRAM Cell. J. Electron. Test. Víctor H. Champac, Javier Mesalles, Hector Villacorta, Fabian Vargas
2020	—	`conf`	Analysis and detection of hard-to-detect full open defects in FinFET based SRAM cells. LATS Zahira Perez, Javier Mesalles, Hector Villacorta, Fabian Vargas, Víctor H. Champac
2020	J	`jnl`	Identification of Logic Paths Influenced by Severe Coupling Capacitances. J. Electron. Test. Ivan D. Meza-Ibarra, Víctor H. Champac, Roberto Gómez-Fuentes, Jose R. Noriega-Luna, A. Vera-Marquina
2019	—	`conf`	A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells. LATS Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac
2019	J	`jnl`	An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects. J. Electron. Test. Andres F. Gomez, Víctor H. Champac
2019	B	`conf`	B-open: A New Defect in Nanometer Technologies due to SADP Process. ETS Freddy Forero, Michel Renovell, Víctor H. Champac
2019	—	`conf`	Identification of Logic Paths Influenced by Severe Coupling Capacitances. LATS Ivan D. Meza-Ibarra, Víctor H. Champac, Roberto Gómez-Fuentes, Jose R. Noriega-Luna, A. Vera-Marquina
2019	J	`jnl`	Modeling and Detectability of Full Open Gate Defects in FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. Freddy Forero, Hector Villacorta, Michel Renovell, Víctor H. Champac
2018	—	`conf`	A metric-guided gate-sizing methodology for aging guardband reduction. LATS Andres F. Gomez, Roberto Gómez, Víctor H. Champac
2018	C	`conf`	An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations. VLSI-SoC Zahira Perez, Hector Villacorta, Víctor H. Champac
2018	—	`conf`	Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection. VLSI-SoC (Selected Papers) Víctor H. Champac, Andres F. Gomez, Freddy Forero, Kaushik Roy
2018	J	`jnl`	Detectability Challenges of Bridge Defects in FinFET Based Logic Cells. J. Electron. Test. Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac
2018	C	`conf`	Robust Detection of Bridge Defects in STT-MRAM Cells Under Process Variations. VLSI-SoC Andres F. Gomez, Freddy Forero, Kaushik Roy, Víctor H. Champac
2018	J	`jnl`	Selection of Critical Paths for Reliable Frequency Scaling under BTI-Aging Considering Workload Uncertainty and Process Variations Effects. ACM Trans. Design Autom. Electr. Syst. Andres F. Gomez, Víctor H. Champac
2017	—	`conf`	Analysis of short defects in FinFET based logic cells. LATS Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac
2016	—	`conf`	A methodology for NBTI circuit reliability at reduced power consumption using dual supply voltage. LATS Freddy Forero, Andres F. Gomez, Víctor H. Champac
2016	B	`conf`	Behavior and test of open-gate defects in FinFET based cells. ETS Francisco Mesalles, Hector Villacorta, Michel Renovell, Víctor H. Champac
2016	—	`conf`	Critical path selection under NBTI/PBTI aging for adaptive frequency tuning. EWDTS Andres F. Gomez, Víctor H. Champac
2016	J	`jnl`	Early Selection of Critical Paths for Reliable NBTI Aging-Delay Monitoring. IEEE Trans. Very Large Scale Integr. Syst. Andres F. Gomez, Víctor H. Champac
2016	J	`jnl`	Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations. IEEE Trans. Very Large Scale Integr. Syst. Jesús Moreno, Michel Renovell, Víctor H. Champac
2016	J	`jnl`	Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations. Microelectron. Reliab. Andres F. Gomez, Felipe Lavratti, Guilherme Medeiros Machado, M. Sartori, Letícia Maria Veiras Bolzani, Víctor H. Champac, Fabian Vargas
2016	J	`jnl`	Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability. J. Electron. Test. Hector Villacorta, Jaume Segura, Víctor H. Champac
2016	J	`jnl`	Improvement of Negative Bias Temperature Instability Circuit Reliability and Power Consumption Using Dual Supply Voltage. J. Low Power Electron. Freddy Forero, Andres F. Gomez, Víctor H. Champac
2015	C	`conf`	A new sizing approach for lifetime improvement of nanoscale digital circuits due to BTI aging. VLSI-SoC Andres F. Gomez, Víctor H. Champac
2015	Misc	`conf`	An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging. VTS Andres F. Gomez, Leticia B. Poehls, Fabian Vargas, Víctor H. Champac
2015	C	`conf`	Circuit performance optimization for local intra-die process variations using a gate selection metric. VLSI-SoC Víctor H. Champac, Alejandra Nicte-ha Reyes, Andres F. Gomez
2015	—	`conf`	Effective selection of favorable gates in BTI-critical paths to enhance circuit reliability. LATS Andres F. Gomez, Víctor H. Champac
2015	—	`conf`	Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell. LATS Hector Villacorta, Roberto Gómez, Sebastià A. Bota, Jaume Segura, Víctor H. Champac
2015	J	`jnl`	Low V Microelectron. J. Hector Villacorta, Jose Luis Garcia-Gervacio, Jaume Segura, Víctor H. Champac
2015	—	`conf`	Message from the LATS2015 Chairs. LATS Víctor H. Champac, Yervant Zorian, Letícia Maria Bolzani Pöhls, Vishwani D. Agrawal
2015	J	`jnl`	Screening small-delay defects using inter-path correlation to reduce reliability risk. Microelectron. Reliab. Jose Luis Garcia-Gervacio, Alejandro Nocua, Víctor H. Champac
2014	—	`conf`	Analysis of fin height on FinFET SRAM cell hardening. MWSCAS Hector Villacorta, Jaume Segura, Sebastià A. Bota, Víctor H. Champac
2014	Misc	`conf`	Hot topic session 12B: Stay relevant with standards-based DFT. VTS C. J. Clark, Víctor H. Champac
2014	—	`conf`	Possibilities of defect-size magnification for testing resistive-opens in nanometer technologies. LATW Jose Luis Garcia-Gervacio, Jaime Martínez-Castillo, Víctor H. Champac
2014	J	`jnl`	Skew violation verification in digital interconnect signals based on signal addition. IEICE Electron. Express Víctor H. Champac, Hector Villacorta, Nestor Hernandez, Joan Figueras
2013	—	`conf`	Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias. LATW Hector Villacorta, Jose Luis Garcia-Gervacio, Víctor H. Champac, Sebastià A. Bota, Jaime Martínez-Castillo, Jaume Segura
2013	J	`jnl`	Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion. J. Electron. Test. Julio César Vázquez, Víctor H. Champac, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira
2013	J	`jnl`	Reliability Analysis of Small-Delay Defects Due to Via Narrowing in Signal Paths. IEEE Des. Test Hector Villacorta, Charles F. Hawkins, Víctor H. Champac, Jaume Segura, Roberto Gómez
2012	J	`jnl`	Aging-Aware Power or Frequency Tuning With Predictive Fault Detection. IEEE Des. Test Comput. Jackson Pachito, Celestino V. Martins, Bruno Jacinto, Jorge Semião, Julio César Vázquez, Víctor H. Champac, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2012	—	`conf`	Low voltage testing for interconnect opens under process variations. LATW Jesús Moreno, Víctor H. Champac, Michel Renovell
2012	J	`jnl`	Resistive bridge defect detection enhancement under parameter variations combining Low V Microelectron. Reliab. Hector Villacorta, Víctor H. Champac, Sebastià A. Bota, Jaume Segura
2012	Misc	`conf`	Small-delay defects detection under process variation using Inter-Path Correlation. VTS Francisco J. Galarza-Medina, Jose Luis Garcia-Gervacio, Víctor H. Champac, Alex Orailoglu
2012	J	`jnl`	Testing of Stuck-Open Faults in Nanometer Technologies. IEEE Des. Test Comput. Víctor H. Champac, Julio Vazquez Hernandez, Salvador Barceló, Roberto Gómez, Chuck Hawkins, Jaume Segura
2011	J	`jnl`	12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011. J. Low Power Electron. Víctor H. Champac, Fernanda Gusmão de Lima Kastensmidt, Letícia Maria Veiras Bolzani Poehls, Fabian Vargas, Yervant Zorian
2011	Misc	`conf`	A new methodology for realistic open defect detection probability evaluation under process variations. VTS Jesús Moreno, Víctor H. Champac, Michel Renovell
2011	Misc	`conf`	Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors. VTS Celestino V. Martins, Jorge Semião, Julio César Vázquez, Víctor H. Champac, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2011	J	`jnl`	Computing the Detection Probability for Small Delay Defects of Nanometer ICs. J. Electron. Test. Jose Luis Garcia-Gervacio, Víctor H. Champac
2010	J	`jnl`	Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals. IEEE Trans. Very Large Scale Integr. Syst. Víctor H. Champac, Victor Avendaño, Joan Figueras
2010	B	`conf`	Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs. ETS Jose Luis Garcia-Gervacio, Víctor H. Champac
2010	Misc	`conf`	Low-sensitivity to process variations aging sensor for automotive safety-critical applications. VTS Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Isabel Maria Cacho Teixeira, Marcelino B. Santos, João Paulo Teixeira
2010	C	`conf`	Predictive error detection by on-line aging monitoring. IOLTS Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira
2010	A	`conf`	Programmable aging sensor for automotive safety-critical applications. DATE Julio César Vázquez, Víctor H. Champac, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira
2010	—	`conf`	Reliability analysis of small delay defects in vias located in signal paths. LATW Hector Villacorta, Víctor H. Champac, Chuck Hawkins, Jaume Segura
2009	—	`conf`	A modern look at the CMOS stuck-open fault. LATW Roberto Gómez, Víctor H. Champac, Chuck Hawkins, Jaume Segura
2009	C	`conf`	Built-in aging monitoring for safety-critical applications. IOLTS Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira
2009	C	`conf`	Detectability analysis of small delays due to resistive opens considering process variations. IOLTS Jose Luis Garcia-Gervacio, Víctor H. Champac
2009	Misc	`conf`	Stuck-Open Fault Leakage and Testing in Nanometer Technologies. VTS Julio César Vázquez, Víctor H. Champac, Chuck Hawkins, Jaume Segura
2008	J	`jnl`	A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines. J. Electron. Test. Roberto Gómez, Alejandro Girón, Víctor H. Champac
2008	C	`conf`	A design methodology for logic paths tolerant to local intra-die variations. ISCAS Daniel Iparraguirre-Cardenas, Jose Luis Garcia-Gervacio, Víctor H. Champac
2008	—	`conf`	Testing Skew and Logic Faults in SoC Interconnects. ISVLSI Nestor Hernandez, Víctor H. Champac
2007	J	`jnl`	Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. Antonio Zenteno Ramírez, Guillermo Espinosa, Víctor H. Champac
2005	—	`conf`	Test of Interconnection Opens Considering Coupling Signals. DFT Roberto Gómez, Alejandro Girón, Víctor H. Champac
2005	B	`conf`	Testing of resistive opens in CMOS latches and flip-flops. ETS Víctor H. Champac, Antonio Zenteno, José L. Garcia
2004	—	`conf`	Analysis and Attenuation Proposal in Ground Bounce. Asian Test Symposium Antonio Zenteno, Víctor H. Champac, Michel Renovell, Florence Azaïs
2004	J	`jnl`	Guest Editorial. J. Electron. Test. Fabian Vargas, Víctor H. Champac
2004	B	`conf`	Signal integrity verification using high speed monitors. ETS Victor Avendaño, Víctor H. Champac, Joan Figueras
2003	J	`jnl`	Guest Editorial. J. Electron. Test. Víctor H. Champac, Ingrid Jansch-Pôrto
2003	—	`conf`	Signal integrity loss in bus lines due to open shielding defects. ETW Victor Avendaño, Víctor H. Champac, Joan Figueras
2002	—	`conf`	A new technique for noise-tolerant pipelined dynamic digital circuits. ISCAS (4) Fernando Mendoza-Hernandez, Mónico Linares Aranda, Víctor H. Champac, Alejandro Díaz-Sánchez
2002	—	`conf`	Behavior Analysis and Testing of Resistive Opens in the Clock Circuitry of Memory Elements. LATW Antonio Zenteno, Víctor H. Champac, Jaime Ramírez-Angulo
2001	J	`jnl`	Detectability Conditions of Full Opens in the Interconnections. J. Electron. Test. Antonio Zenteno, Víctor H. Champac, Joan Figueras
2001	—	`conf`	Dynamic Signal X-Y Zoning and its Applicability to Detect Time Critical Defects in the Digital Domain. LATW Anotnio Zenteno, Víctor H. Champac, Joan Figueras
2001	J	`jnl`	Guest Editorial. J. Electron. Test. Marcelo Lubaszewski, Víctor H. Champac
2001	Misc	`conf`	Resistive Opens in a Class of CMOS Latches: Analysis and DFT. VTS Antonio Zenteno, Víctor H. Champac
2001	—	`conf`	Test of Data Retention Faults Sensing the Bit Line with a DFT Bases Differential Amplifier. LATW Víctor H. Champac, Victor Avendaño, Gordana Jovanovic-Dolecek
2000	J	`jnl`	CGTDEMO - educational software for the central limit theorem. ACM SIGCSE Bull. Gordana Jovanovic-Dolecek, Víctor H. Champac
2000	Misc	`conf`	Detectability Conditions for Interconnection Open Defect. VTS Víctor H. Champac, Antonio Zenteno
2000	—	`conf`	Detectability Dependency on Test Generation Process for Interconnection Opens. LATW Antonio Zenteno, Víctor H. Champac, Joan Figueras
1999	J	`jnl`	IDDQ Testing of Opens in CMOS SRAMs. J. Electron. Test. Víctor H. Champac, José Castillejos, Joan Figueras
1998	—	`conf`	A Graph-Oriented CAD Tool for Establishing the Topological Diagnostic Conditions of Analogue Circuits. SBCCI Arturo Sarmiento-Reyes, Miguel Ángel Gutiérrez de Anda, Víctor H. Champac
1998	Misc	`conf`	IDDQ Testing of Opens in CMOS SRAMs. VTS Víctor H. Champac, José Castillejos, Joan Figueras
1997	J	`jnl`	Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects. VLSI Design Víctor H. Champac, Joan Figueras
1995	Misc	`conf`	Testability of floating gate defects in sequential circuits. VTS Víctor H. Champac, Joan Figueras
1994	J	`jnl`	Electrical model of the floating gate defect in CMOS ICs: implications on I IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Víctor H. Champac, Antonio Rubio, Joan Figueras
1993	—	`conf`	Analysis of the Floating Gate Defect in CMOS. DFT Víctor H. Champac, Antonio Rubio, Joan Figueras
1992	J	`jnl`	Quiescent current analysis and experimentation of defective CMOS circuits. J. Electron. Test. Jaume A. Segura, Víctor H. Champac, Rosa Rodríguez-Montañés, Joan Figueras, J. A. Rubio
1991	A	`conf`	Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS. ITC Rosa Rodríguez-Montañés, Jaume A. Segura, Víctor H. Champac, Joan Figueras, J. A. Rubio