Volnei A. Pedroni

24 papers C 6Journal 5Unranked 12
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 192-Channel 1D CNN-Based Neural Feature Extractor in 65nm CMOS for Brain-Machine Interfaces.
IEEE Trans. Biomed. Circuits Syst.
Steven P. Bulfer, Jorge Gámez, Albert Yan-Huang, Benyamin Allahgholizadeh Haghi, Volnei A. Pedroni, Richard A. Andersen, Azita Emami
2018 J jnl
A reliable and energy-efficient classifier combination scheme for intrusion detection in embedded systems.
Comput. Secur.
Eduardo Viegas, Altair Olivo Santin, Luiz Oliveira, André França, Ricardo P. Jasinski, Volnei A. Pedroni
2017 J jnl
Towards an Energy-Efficient Anomaly-Based Intrusion Detection Engine for Embedded Systems.
IEEE Trans. Computers
Eduardo Viegas, Altair Olivo Santin, André França, Ricardo P. Jasinski, Volnei A. Pedroni, Luiz S. Oliveira
2015 C conf
Introducing deglitched-feedback plus convergent encoding for straight hardware implementation of asynchronous finite state machines.
ISCAS
Volnei A. Pedroni
2015 C conf
The energy cost of network security: A hardware vs. software comparison.
ISCAS
André Luiz Pereira de França, Ricardo P. Jasinski, Paulo Cemin, Volnei A. Pedroni, Altair Olivo Santin
2015 C conf
XOR-decomposition principle and its use to build a glitch-free maximum-speed arbitrary binary waveform generator and deglitcher.
ISCAS
Volnei A. Pedroni
2014 — conf
Detailed analysis of implementation options for timed finite state machines in hardware.
MWSCAS
Volnei A. Pedroni
2012 — conf
A new hardware coprocessor for accelerating Notification-Oriented applications.
FPT
Eduardo Peters, Ricardo P. Jasinski, Volnei A. Pedroni, Jean Marcelo Simão
2011 C conf
A very efficient single-iteration oldest-out data sorter.
ISCAS
Volnei A. Pedroni, Ricardo P. Jasinski, Ricardo U. Pedroni
2010 — conf
Achieving near-MLD performance with soft information-set decoders implemented in FPGAs.
APCCAS
Antonio Gortan, Ricardo P. Jasinski, Walter Godoy Jr., Volnei A. Pedroni
2010 — conf
An Improved GF(2) Matrix Inverter with Linear Time Complexity.
ReConFig
Ricardo P. Jasinski, Volnei A. Pedroni, Antonio Gortan, Walter Godoy Jr.
2010 — conf
Analysis and Preliminary Measurements of Radiated Emissions in an Asynchronous Circuit versus its Synchronous Counterpart.
ReConFig
Rui A. L. de Cristo, Ricardo P. Jasinski, Volnei A. Pedroni
2010 — conf
Panning sorter: A minimal-size architecture for hardware implementation of 2D Data Sorting Coprocessors.
APCCAS
Volnei A. Pedroni, Ricardo P. Jasinski, Ricardo U. Pedroni
2007 — ed.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007
SBCCI
Antonio Petraglia, Volnei A. Pedroni, Gert Cauwenberghs
2006 C conf
PLL-less clock multiplier with self-adjusting phase symmetry.
ISCAS
Volnei A. Pedroni, Ricardo U. Pedroni
2006 C conf
Phase sampling: a new approach to the design of LF direct digital frequency synthesizers.
ISCAS
Volnei A. Pedroni
2005 J jnl
Output stage based high-resolution min/max and rank-order filters.
IEEE Trans. Circuits Syst. II Express Briefs
Volnei A. Pedroni, Bruno U. Pedroni
2004 — conf
Compact Hamming-Comparator-based rank order filter for digital VLSI and FPGA implementations.
ISCAS (2)
Volnei A. Pedroni
2004 — conf
Taking advantage of LVDS input buffers to implement sigma-delta A/D converters in FPGAs.
ISCAS (1)
Fabio Sousa, Volker Mauer, Neimar Duarte, Ricardo P. Jasinski, Volnei A. Pedroni
2003 — conf
High-Resolution WTA-MAX Circuit for Large Networks.
VLSI
Volnei A. Pedroni
2003 — conf
Teaching Design-Oriented VHDL.
MSE
Volnei A. Pedroni
1997 J jnl
A low-power CMOS analog vector quantizer.
IEEE J. Solid State Circuits
Gert Cauwenberghs, Volnei A. Pedroni
1994 — conf
A Charge-Based Parallel Analog Vector Quantizer.
NIPS
Gert Cauwenberghs, Volnei A. Pedroni
1993 — conf
Learning in the hypercube.
ICNN
Volnei A. Pedroni, Amnon Yariv