Vojtech Mrazek

94 papers A* 2A 19B 4C 10Misc 1Journal 40Unranked 17

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	ApproxGNN: A Pretrained GNN for Parameter Prediction in Design Space Exploration for Approximate Computing. ICCAD Ondrej Vlcek, Vojtech Mrazek
2025	J	`jnl`	ApproxGNN: A Pretrained GNN for Parameter Prediction in Design Space Exploration for Approximate Computing. CoRR Ondrej Vlcek, Vojtech Mrazek
2025	J	`jnl`	Arbitrary Precision Printed Ternary Neural Networks with Holistic Evolutionary Approximation. CoRR Vojtech Mrazek, Konstantinos Balaskas, Paula Carolina Lozano Duarte, Zdenek Vasícek, Mehdi B. Tahoori, Georgios Zervakis
2025	C	`conf`	AxMED: Formal Analysis and Automated Design of Approximate Median Filters using BDDs. ISCAS Vojtech Mrazek, Zdenek Vasícek
2025	J	`jnl`	AxMED: Formal Analysis and Automated Design of Approximate Median Filters using BDDs. CoRR Vojtech Mrazek, Zdenek Vasícek
2025	—	`conf`	Efficient Scheduling of Transformer Neural Network Computation for Edge-AI Deployment. GECCO Companion David Sedlak, Jan Klhufek, Vojtech Mrazek, Zdenek Vasícek
2025	C	`conf`	Inference Energy Analysis in Context of Hardware-Aware NAS. DDECS Michal Pinos, Jan Klhufek, Vojtech Mrazek, Lukás Sekanina
2025	A	`conf`	Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference Accelerators. DATE Filip Masar, Vojtech Mrazek, Lukás Sekanina
2025	J	`jnl`	Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference Accelerators. CoRR Filip Masar, Vojtech Mrazek, Lukás Sekanina
2025	B	`conf`	Multi-objective Evolutionary Design of Explainable EEG Classifier. EuroGP Martin Hurta, Anna Ovesna, Vojtech Mrazek, Lukás Sekanina
2025	J	`jnl`	TransInferSim: Toward Fast and Accurate Evaluation of Embedded Hardware Accelerators for Transformer Networks. IEEE Access Jan Klhufek, Alberto Marchisio, Vojtech Mrazek, Lukás Sekanina, Muhammad Shafique
2024	B	`conf`	ApproxDARTS: Differentiable Neural Architecture Search with Approximate Multipliers. IJCNN Michal Pinos, Lukás Sekanina, Vojtech Mrazek
2024	J	`jnl`	ApproxDARTS: Differentiable Neural Architecture Search with Approximate Multipliers. CoRR Michal Pinos, Lukás Sekanina, Vojtech Mrazek
2024	A	`conf`	Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. DATE Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
2024	J	`jnl`	Energy Complexity of Convolutional Neural Networks. Neural Comput. Jirí Síma, Petra Vidnerová, Vojtech Mrazek
2024	A	`conf`	Evolutionary Approximation of Ternary Neurons for On-sensor Printed Neural Networks. ICCAD Vojtech Mrazek, Argyris Kokkinis, Panagiotis Papanikolaou, Zdenek Vasícek, Kostas Siozios, Georgios Tzimpragos, Mehdi B. Tahoori, Georgios Zervakis
2024	J	`jnl`	Evolutionary Approximation of Ternary Neurons for On-sensor Printed Neural Networks. CoRR Vojtech Mrazek, Argyris Kokkinis, Panagiotis Papanikolaou, Zdenek Vasícek, Kostas Siozios, Georgios Tzimpragos, Mehdi Baradaran Tahoori, Georgios Zervakis
2024	C	`conf`	Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. DDECS Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
2024	J	`jnl`	Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. CoRR Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
2023	A	`conf`	ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. DATE Martin Hurta, Vojtech Mrazek, Michaela Drahosova, Lukás Sekanina
2023	J	`jnl`	Acceleration Techniques for Automated Design of Approximate Convolutional Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. Michal Pinos, Vojtech Mrazek, Filip Vaverka, Zdenek Vasícek, Lukás Sekanina
2023	C	`conf`	Approximation of Hardware Accelerators driven by Machine-Learning Models : (Embedded Tutorial). DDECS Vojtech Mrazek
2023	A	`conf`	Effective EEG Feature Selection for Interpretable MDD (Major Depressive Disorder) Classification. GECCO Vojtech Mrazek, Soyiba Jawed, Muhammad Arif, Aamir Saeed Malik
2023	—	`conf`	Energy Complexity Model for Convolutional Neural Networks. ICANN (10) Jirí Síma, Petra Vidnerová, Vojtech Mrazek
2023	C	`conf`	MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. DDECS Martin Hurta, Vojtech Mrazek, Michaela Drahosova, Lukás Sekanina
2023	C	`conf`	Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits. DDECS Michal Pinos, Vojtech Mrazek, Lukás Sekanina
2023	A	`conf`	Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. ICCAD Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
2023	J	`jnl`	autoXFPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. CoRR Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
2022	C	`conf`	ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators. DDECS Jan Klhufek, Vojtech Mrazek
2022	J	`jnl`	ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators. CoRR Jan Klhufek, Vojtech Mrazek
2022	C	`conf`	Designing Approximate Arithmetic Circuits with Combined Error Constraints. DSD Milan Ceska, Jirí Matyás, Vojtech Mrazek, Tomás Vojnar
2022	J	`jnl`	Designing Approximate Arithmetic Circuits with Combined Error Constraints. CoRR Milan Ceska, Jirí Matyás, Vojtech Mrazek, Tomás Vojnar
2022	—	`conf`	Evolutionary Design of Reduced Precision Preprocessor for Levodopa-Induced Dyskinesia Classifier. PPSN (1) Martin Hurta, Michaela Drahosova, Vojtech Mrazek
2022	J	`jnl`	Evolutionary approximation and neural architecture search. Genet. Program. Evolvable Mach. Michal Pinos, Vojtech Mrazek, Lukás Sekanina
2022	—	`conf`	Optimization of BDD-based Approximation Error Metrics Calculations. ISVLSI Vojtech Mrazek
2022	J	`jnl`	Optimization of BDD-based Approximation Error Metrics Calculations. CoRR Vojtech Mrazek
2022	J	`jnl`	RoHNAS: A Neural Architecture Search Framework With Conjoint Optimization for Adversarial Robustness and Hardware Efficiency of Convolutional and Capsule Networks. IEEE Access Alberto Marchisio, Vojtech Mrazek, Andrea Massa, Beatrice Bussolino, Maurizio Martina, Muhammad Shafique
2022	J	`jnl`	RoHNAS: A Neural Architecture Search Framework with Conjoint Optimization for Adversarial Robustness and Hardware Efficiency of Convolutional and Capsule Networks. CoRR Alberto Marchisio, Vojtech Mrazek, Andrea Massa, Beatrice Bussolino, Maurizio Martina, Muhammad Shafique
2022	J	`jnl`	SagTree: Towards efficient mutation in evolutionary circuit approximation. Swarm Evol. Comput. Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
2021	C	`ed.`	24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021 DDECS Muhammad Shafique, Andreas Steininger, Lukás Sekanina, Milos Krstic, Goran Stojanovic, Vojtech Mrazek
2021	J	`jnl`	DESCNet: Developing Efficient Scratchpad Memories for Capsule Network Hardware. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alberto Marchisio, Vojtech Mrazek, Muhammad Abdullah Hanif, Muhammad Shafique
2021	B	`conf`	Evolutionary Neural Architecture Search Supporting Approximate Multipliers. EuroGP Michal Pinos, Vojtech Mrazek, Lukás Sekanina
2021	J	`jnl`	Evolutionary Neural Architecture Search Supporting Approximate Multipliers. CoRR Michal Pinos, Vojtech Mrazek, Lukás Sekanina
2021	J	`jnl`	FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators. IEEE Trans. Very Large Scale Integr. Syst. Alberto Marchisio, Vojtech Mrazek, Muhammad Abdullah Hanif, Muhammad Shafique
2021	J	`jnl`	Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design. Genet. Program. Evolvable Mach. David Hodan, Vojtech Mrazek, Zdenek Vasícek
2020	Misc	`conf`	A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress. CODES+ISSS Alessio Colucci, Alberto Marchisio, Beatrice Bussolino, Vojtech Mrazek, Maurizio Martina, Guido Masera, Muhammad Shafique
2020	J	`jnl`	Adaptive Verifiability-Driven Strategy for Evolutionary Approximation of Arithmetic Circuits. CoRR Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
2020	J	`jnl`	Adaptive verifiability-driven strategy for evolutionary approximation of arithmetic circuits. Appl. Soft Comput. Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
2020	A*	`conf`	ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. DAC Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
2020	J	`jnl`	ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. CoRR Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
2020	J	`jnl`	DESCNet: Developing Efficient Scratchpad Memories for Capsule Network Hardware. CoRR Alberto Marchisio, Vojtech Mrazek, Muhammad Abdullah Hanif, Muhammad Shafique
2020	J	`jnl`	Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. IEEE Trans. Very Large Scale Integr. Syst. Mohammad Saeed Ansari, Vojtech Mrazek, Bruce F. Cockburn, Lukás Sekanina, Zdenek Vasícek, Jie Han
2020	J	`jnl`	Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek
2020	A	`conf`	NASCaps: A Framework for Neural Architecture Search to Optimize the Accuracy and Hardware Efficiency of Convolutional Capsule Networks. ICCAD Alberto Marchisio, Andrea Massa, Vojtech Mrazek, Beatrice Bussolino, Maurizio Martina, Muhammad Shafique
2020	J	`jnl`	NASCaps: A Framework for Neural Architecture Search to Optimize the Accuracy and Hardware Efficiency of Convolutional Capsule Networks. CoRR Alberto Marchisio, Andrea Massa, Vojtech Mrazek, Beatrice Bussolino, Maurizio Martina, Muhammad Shafique
2020	A	`conf`	ReD-CaNe: A Systematic Methodology for Resilience Analysis and Design of Capsule Networks under Approximations. DATE Alberto Marchisio, Vojtech Mrazek, Muhammad Abdullah Hanif, Muhammad Shafique
2020	A	`conf`	Satisfiability Solving Meets Evolutionary Optimisation in Designing Approximate Circuits. SAT Milan Ceska, Jirí Matyás, Vojtech Mrazek, Tomás Vojnar
2020	J	`jnl`	Semantically-Oriented Mutation Operator in Cartesian Genetic Programming for Evolutionary Circuit Design. CoRR David Hodan, Vojtech Mrazek, Zdenek Vasícek
2020	A	`conf`	Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design. GECCO David Hodan, Vojtech Mrazek, Zdenek Vasícek
2020	A	`conf`	TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. DATE Filip Vaverka, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
2020	J	`jnl`	TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. CoRR Filip Vaverka, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
2020	—	`conf`	Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. AICAS Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek
2020	J	`jnl`	Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. CoRR Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek
2019	A	`conf`	ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. ICCAD Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Abdullah Hanif, Muhammad Shafique
2019	J	`jnl`	ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. CoRR Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Abdullah Hanif, Muhammad Shafique
2019	A	`conf`	Automated Circuit Approximation Method Driven by Data Distribution. DATE Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
2019	J	`jnl`	Automated Circuit Approximation Method Driven by Data Distribution. CoRR Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
2019	—	`ch.`	Automated Search-Based Functional Approximation for Digital Circuits. Approximate Circuits Lukás Sekanina, Zdenek Vasícek, Vojtech Mrazek
2019	J	`jnl`	Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques. IEEE Trans. Very Large Scale Integr. Syst. Vojtech Mrazek, Lukás Sekanina, Roland Dobai, Marek Sýs, Petr Svenda
2019	J	`jnl`	ReD-CaNe: A Systematic Methodology for Resilience Analysis and Design of Capsule Networks under Approximations. CoRR Alberto Marchisio, Vojtech Mrazek, Muhammad Abdullah Hanif, Muhammad Shafique
2019	A*	`conf`	autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. DAC Vojtech Mrazek, Muhammad Abdullah Hanif, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
2019	J	`jnl`	autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. CoRR Vojtech Mrazek, Muhammad Abdullah Hanif, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
2018	—	`conf`	ADAC: Automated Design of Approximate Circuits. CAV (1) Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
2018	—	`conf`	Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives. ICECS Lukás Sekanina, Vojtech Mrazek, Zdenek Vasícek
2018	—	`conf`	Design of Quality-Configurable Approximate Multipliers Suitable for Dynamic Environment. AHS Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
2018	—	`conf`	Evolutionary design of large approximate adders optimized for various error criteria. GECCO (Companion) Vojtech Mrazek, Zdenek Vasícek
2018	A	`conf`	Evolving boolean functions for fast and efficient randomness testing. GECCO Vojtech Mrazek, Marek Sýs, Zdenek Vasícek, Lukás Sekanina, Vashek Matyas
2018	J	`jnl`	Role of circuit representation in evolutionary design of energy-efficient approximate circuits. IET Comput. Digit. Tech. Vojtech Mrazek, Zdenek Vasícek, Radek Hrbacek
2018	J	`jnl`	Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error. IEEE Trans. Very Large Scale Integr. Syst. Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Honglan Jiang, Jie Han
2017	—	`conf`	Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. ISVLSI Muhammad Shafique, Rehan Hafiz, Muhammad Usama Javed, Sarmad Abbas, Lukás Sekanina, Zdenek Vasícek, Vojtech Mrazek
2017	A	`conf`	Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished. ICCAD Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
2017	A	`conf`	EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. DATE Vojtech Mrazek, Radek Hrbacek, Zdenek Vasícek, Lukás Sekanina
2017	—	`conf`	Parallel optimization of transistor level circuits using cartesian genetic programming. GECCO (Companion) Vojtech Mrazek, Zdenek Vasícek
2017	A	`conf`	Towards low power approximate DCT architecture for HEVC standard. DATE Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
2017	J	`jnl`	Trading between quality and non-functional properties of median filter in embedded systems. Genet. Program. Evolvable Mach. Zdenek Vasícek, Vojtech Mrazek
2016	—	`conf`	Automatic design of approximate circuits by means of multi-objective evolutionary algorithms. DTIS Radek Hrbacek, Vojtech Mrazek, Zdenek Vasícek
2016	—	`conf`	Automatic design of arbitrary-size approximate sorting networks with error guarantee. PATMOS Vojtech Mrazek, Zdenek Vasícek
2016	A	`conf`	Design of power-efficient approximate multipliers for approximate artificial neural networks. ICCAD Vojtech Mrazek, Syed Shakib Sarwar, Lukás Sekanina, Zdenek Vasícek, Kaushik Roy
2016	—	`conf`	Evolutionary design of polymorphic gates using ambipolar transistors. SSCI Jan Nevoral, Richard Ruzicka, Vojtech Mrazek
2016	—	`conf`	Evolutionary functional approximation of circuits implemented into FPGAs. SSCI Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
2015	C	`conf`	Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers. EUC Vojtech Mrazek, Zdenek Vasícek
2015	—	`conf`	Evolutionary Approximation of Software for Embedded Systems: Median Function. GECCO (Companion) Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
2015	B	`conf`	Evolutionary Design of Transistor Level Digital Circuits Using Discrete Simulation. EuroGP Vojtech Mrazek, Zdenek Vasícek
2014	—	`conf`	Acceleration of transistor-level evolution using Xilinx Zynq Platform. ICES Vojtech Mrazek, Zdenek Vasícek