Vojin G. Oklobdzija

85 papers A 9C 15Misc 1Journal 31Unranked 27

Year	Rank	Type	Title / Venue / Authors
2015	C	`conf`	Minimizing Energy by Achieving Optimal Sparseness in Parallel Adders. ARITH Mustafa Aktan, Dursun Baran, Vojin G. Oklobdzija
2011	—	`conf`	A Quick Method for Energy Optimized Gate Sizing of Digital Circuits. PATMOS Mustafa Aktan, Dursun Baran, Vojin G. Oklobdzija
2011	C	`conf`	Multiplier structures for low power applications in deep-CMOS. ISCAS Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija
2010	—	`conf`	Computing at the ultimate low-energy limits. SBCCI Vojin G. Oklobdzija
2010	—	`conf`	Design of a link-controller architecture for multiple serial link protocols. SoCC Lei Wang, Pawankumar Hegde, Vishal Nawathe, Roman Staszewski, Poras T. Balsara, Vojin G. Oklobdzija
2010	A	`conf`	Energy efficient implementation of parallel CMOS multipliers with improved compressors. ISLPED Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija
2010	J	`jnl`	Energy-Efficient Design Methodologies: High-Performance VLSI Adders. IEEE J. Solid State Circuits Bart R. Zeydel, Dursun Baran, Vojin G. Oklobdzija
2010	J	`jnl`	Low-Power Soft Error Hardened Latch. J. Low Power Electron. Hossein Karimiyan Alidash, Vojin G. Oklobdzija
2010	A	`ed.`	Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010 ISLPED Vojin G. Oklobdzija, Barry Pangle, Naehyuck Chang, Naresh R. Shanbhag, Chris H. Kim
2009	—	`conf`	A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR). PATMOS Milena Vratonjic, Matthew M. Ziegler, George Gristede, Victor V. Zyuban, Thomas Mitchell, Ee Cho, Chandu Visweswariah, Vojin G. Oklobdzija
2009	—	`conf`	Low-Power Soft Error Hardened Latch. PATMOS Hossein Karimiyan Alidash, Vojin G. Oklobdzija
2008	—	`conf`	Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements. PATMOS Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija
2008	J	`jnl`	Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija
2008	A	`ed.`	Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008 ISLPED Vijaykrishnan Narayanan, C. P. Ravikumar, Jörg Henkel, Ali Keshavarzi, Vojin G. Oklobdzija, Barry M. Pangrle
2008	—	`ch.`	Reduced Instruction Set Computing. Wiley Encyclopedia of Computer Science and Engineering Vojin G. Oklobdzija
2007	—	`conf`	Logic Style Comparison for Ultra Low Power Operation in 65nm Technology. PATMOS Mandeep Singh, Christophe Giacomotto, Bart R. Zeydel, Vojin G. Oklobdzija
2007	J	`jnl`	The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements. IEEE J. Solid State Circuits Christophe Giacomotto, Nikola Nedovic, Vojin G. Oklobdzija
2006	J	`jnl`	A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS. IEEE J. Solid State Circuits Steven K. Hsu, Sanu K. Mathew, Mark A. Anders, Bart R. Zeydel, Vojin G. Oklobdzija, Ram K. Krishnamurthy, Shekhar Y. Borkar
2006	—	`conf`	Circuit Design Style for Energy Efficiency: LSDL and Compound Domino. PATMOS Xiao Yan Yu, Robert K. Montoye, Kevin J. Nowka, Bart R. Zeydel, Vojin G. Oklobdzija
2006	—	`conf`	Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design. PATMOS Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija
2006	J	`jnl`	Energy optimization of pipelined digital systems using circuit sizing and supply scaling. IEEE Trans. Very Large Scale Integr. Syst. Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija
2006	—	`conf`	Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations. PATMOS Christophe Giacomotto, Nikola Nedovic, Vojin G. Oklobdzija
2006	—	`conf`	Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations. PATMOS Bart R. Zeydel, Vojin G. Oklobdzija
2005	—	`conf`	A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers. PATMOS Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija
2005	C	`conf`	Architectural Considerations for Energy Efficiency. ICCD Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija
2005	J	`jnl`	Comparison of high-performance VLSI adders in the energy-delay space. IEEE Trans. Very Large Scale Integr. Syst. Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy
2005	J	`jnl`	Dual-edge triggered storage elements and clocking strategy for low-power systems. IEEE Trans. Very Large Scale Integr. Syst. Nikola Nedovic, Vojin G. Oklobdzija
2005	C	`conf`	Efficient Mapping of Addition Recurrence Algorithms in CMOS. IEEE Symposium on Computer Arithmetic Bart R. Zeydel, Theo T. J. H. Kluter, Vojin G. Oklobdzija
2005	C	`conf`	Low- and Ultra Low-Power Arithmetic Units: Design and Comparison. ICCD Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija
2005	—	`ed.`	Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, Marina del Rey, CA, USA, October 24-26, 2005 Circuits, Signals, and Systems Vojin G. Oklobdzija
2004	J	`jnl`	A test circuit for measurement of clocked storage element characteristics. IEEE J. Solid State Circuits Nikola Nedovic, William W. Walker, Vojin G. Oklobdzija
2003	—	`conf`	An efficient transistor optimizer for custom circuits. ISCAS (5) Xiao Yan Yu, Vojin G. Oklobdzija, William W. Walker
2003	—	`conf`	Area-time optimal adder with relative placement generator. ISCAS (5) Aamir A. Farooqui, Vojin G. Oklobdzija, Sadiq M. Sait
2003	J	`jnl`	Clocking and clocked storage elements in a multi-gigahertz environment. IBM J. Res. Dev. Vojin G. Oklobdzija
2003	—	`conf`	Energy Optimization of High-Performance Circuits. PATMOS Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija
2003	—	`conf`	Energy minimization method for optimal energy-delay extraction. ESSCIRC Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija
2003	C	`conf`	Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders. IEEE Symposium on Computer Arithmetic Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy
2003	C	`conf`	Tutorial: Design of Power Efficient VLSI Arithmetic: Speed and Power Trade-Offs. IEEE Symposium on Computer Arithmetic Vojin G. Oklobdzija, Ram Krishnamurthy
2002	—	`conf`	Clocking and Clocked Storage Elements in Multi-GHz Environment. PATMOS Vojin G. Oklobdzija
2002	—	`conf`	Comparative analysis of double-edge versus single-edge triggered clocked storage elements. ISCAS (5) Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
2002	A	`conf`	Conditional pre-charge techniques for power-efficient dual-edge clocking. ISLPED Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
2002	A	`conf`	Future directions in clocking multi-ghz systems. ISLPED Vojin G. Oklobdzija, Jens Sparsø
2002	—	`conf`	Optimal Sequencing Energy Allocation for CMOS Integrated Systems. ISQED Martin Saint-Laurent, Vojin G. Oklobdzija, Simon S. Singh, Madhavan Swaminathan
2002	—	`conf`	Performance Comparison of VLSI Adders Using Logical Effort. PATMOS Hoang Q. Dao, Vojin G. Oklobdzija
2001	A	`conf`	Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation. ISLPED Hoang Q. Dao, Kevin J. Nowka, Vojin G. Oklobdzija
2001	—	`conf`	Conditional techniques for low power consumption flip-flops. ICECS Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
2001	C	`conf`	Timing Characterization of Dual-edge Triggered Flip-flops. ICCD Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
2000	J	`jnl`	Clocked CMOS adiabatic logic with integrated single-phase power-clock supply. IEEE Trans. Very Large Scale Integr. Syst. Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current
2000	C	`conf`	Dynamic Flip-Flop with Improved Power. ICCD Nikola Nedovic, Vojin G. Oklobdzija
2000	—	`conf`	Hybrid latch Flip-Flop with Improved Power Efficiency. SBCCI Nikola Nedovic, Vojin G. Oklobdzija
2000	J	`jnl`	Improved sense-amplifier-based flip-flop: design and measurements. IEEE J. Solid State Circuits Borivoje Nikolic, Vojin G. Oklobdzija, Vladimir Stojanovic, Wenyan Jia, James Kar-Shing Chiu, Michael Ming-Tak Leung
2000	—	`conf`	Partitioned Branch Condition Resolution Logic. SBCCI Aamir A. Farooqui, K. Wayne Current, Vojin G. Oklobdzija
1999	J	`jnl`	Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems. IEEE J. Solid State Circuits Vladimir Stojanovic, Vojin G. Oklobdzija
1999	—	`conf`	VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing. Great Lakes Symposium on VLSI Aamir A. Farooqui, Vojin G. Oklobdzija
1998	A	`conf`	A unified approach in the analysis of latches and flip-flops for low-power systems. ISLPED Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa
1998	C	`conf`	Comparative analysis of latches and flip-flops for high-performance systems. ICCD Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa
1998	J	`jnl`	Optimal Circuits for Parallel Multipliers. IEEE Trans. Computers Paul F. Stelling, Charles U. Martel, Vojin G. Oklobdzija, R. Ravi
1997	A	`conf`	Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results. ISLPED Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current
1997	J	`jnl`	Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]. IEEE J. Solid State Circuits Vojin G. Oklobdzija, Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
1997	C	`conf`	Implementing Multiply-Accumulate Operation in Multiplication Time. IEEE Symposium on Computer Arithmetic Paul F. Stelling, Vojin G. Oklobdzija
1996	J	`jnl`	A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach. IEEE Trans. Computers Vojin G. Oklobdzija, David Villeger, Simon S. Liu
1996	J	`jnl`	An ECL gate with improved speed and low power in a BiCMOS process. IEEE J. Solid State Circuits Vojin G. Oklobdzija
1996	J	`jnl`	Design strategies for optimal hybrid final adders in a parallel multiplier. J. VLSI Signal Process. Paul F. Stelling, Vojin G. Oklobdzija
1996	J	`jnl`	Efficient realizations of squaring circuit and reciprocal used in adaptive sample rate notch filters. J. VLSI Signal Process. Richard H. Strandberg, Luis G. Bustamante, Vojin G. Oklobdzija, Michael A. Soderstrand, Jean-Claude Duc
1996	J	`jnl`	Guest editors' introduction. J. VLSI Signal Process. Vojin G. Oklobdzija, Belle Wei
1996	—	`conf`	Low-Energy Logic Circuit Techniques for Multiple-Valued Logic. ISMVL K. Wayne Current, Vojin G. Oklobdzija, Dragan Maksimovic
1995	C	`conf`	Design Strategies for Optimal Multiplier Circuits. IEEE Symposium on Computer Arithmetic Charles U. Martel, Vojin G. Oklobdzija, R. Ravi, Paul F. Stelling
1995	J	`jnl`	Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology. IEEE Trans. Very Large Scale Integr. Syst. Vojin G. Oklobdzija, David Villeger
1995	—	`conf`	Monte Carlo and molecular dynamics simulations using p4. IPPS K. J. Runge, L. P. Lee, J. Correa, Richard Scalettar, Vojin G. Oklobdzija
1995	J	`jnl`	Multithreaded Decoupled Architecture. Int. J. High Speed Comput. Mikhail N. Dorojevets, Vojin G. Oklobdzija
1995	J	`jnl`	Simulations of Interacting Many Body Systems Using P4. Int. J. High Speed Comput. Richard Scalettar, K. J. Runge, J. Correa, P. Lee, Vojin G. Oklobdzija, J. L. Vujic
1994	J	`jnl`	An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis. IEEE Trans. Very Large Scale Integr. Syst. Vojin G. Oklobdzija
1994	J	`jnl`	An integrated multiplier for complex numbers. J. VLSI Signal Process. Vojin G. Oklobdzija, David Villeger, Thierry Soulas
1994	C	`conf`	Determination of Optimal Sizes for a First and Second Level SRAM-DRAM On-Chip Cache Combination. ICCD Rupinder Hundal, Vojin G. Oklobdzija
1994	—	`conf`	High-Performance Computer Arithmetic and Implementations: Introduction. HICSS (1) Vojin G. Oklobdzija
1992	J	`jnl`	Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming. IEEE Trans. Computers Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija
1991	C	`conf`	Delay optimization of carry-skip adders and block carry-lookahead adders. IEEE Symposium on Computer Arithmetic Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija
1991	J	`jnl`	Improved CLA scheme with optimized delay. J. VLSI Signal Process. Brian D. Lee, Vojin G. Oklobdzija
1991	J	`jnl`	Introduction. J. VLSI Signal Process. Vojin G. Oklobdzija, Belle Wei
1988	J	`jnl`	Issues in CPU-coprocessor communication and synchronization. Microprocess. Microprogramming Vojin G. Oklobdzija
1988	J	`jnl`	On Implementing Addition in VLSI Technology. J. Parallel Distributed Comput. Vojin G. Oklobdzija, Earl R. Barnes
1988	Misc	`conf`	VLSI architecture of a real-time Wigner distribution processor for acoustic signals. ICASSP N. M. Marinovic, Vojin G. Oklobdzija, L. Roytman
1985	C	`conf`	Some optimal schemes for ALU implementation in VLSI technology. IEEE Symposium on Computer Arithmetic Vojin G. Oklobdzija, Earl R. Barnes
1984	A	`conf`	Test Generation for FET Switching Circuits. ITC J. Paul Roth, Vojin G. Oklobdzija, John F. Beetem
1982	J	`jnl`	A On-Line Square Root Algorithm. IEEE Trans. Computers Vojin G. Oklobdzija, Milos D. Ercegovac