Vladimir Herdt

67 papers A* 7A 14B 3C 16Journal 10Unranked 14

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	Coverage-Guided Fuzzing for Plan-Based Robotics. ICAART (2) Tim Meywerk, Vladimir Herdt, Rolf Drechsler
2023	C	`conf`	Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification. FDL Milan Funck, Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
2023	A	`conf`	Processor Verification using Symbolic Execution: A RISC-V Case-Study. DATE Niklas Bruns, Vladimir Herdt, Rolf Drechsler
2023	J	`jnl`	Specification-Based Symbolic Execution for Stateful Network Protocol Implementations in IoT. IEEE Internet Things J. Sören Tempel, Vladimir Herdt, Rolf Drechsler
2022	C	`conf`	3D Visualization of Symbolic Execution Traces. FDL Jan Zielasko, Sören Tempel, Vladimir Herdt, Rolf Drechsler
2022	—	`conf`	Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype. ACM Great Lakes Symposium on VLSI Pascal Pieper, Vladimir Herdt, Rolf Drechsler
2022	J	`jnl`	Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges. Sci. China Inf. Sci. Vladimir Herdt, Rolf Drechsler
2022	—	`conf`	Automated Detection of Spatial Memory Safety Violations for Constrained Devices. ASP-DAC Sören Tempel, Vladimir Herdt, Rolf Drechsler
2022	A	`conf`	Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging. DATE Niklas Bruns, Vladimir Herdt, Eyck Jentzsch, Rolf Drechsler
2022	—	`conf`	Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing. ACM Great Lakes Symposium on VLSI Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler
2022	B	`conf`	SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification. ATVA Sören Tempel, Vladimir Herdt, Rolf Drechsler
2022	—	`conf`	Simulation-Based Debugging of Formal Environment Models. MED Tim Meywerk, Arthur Niedzwiecki, Vladimir Herdt, Rolf Drechsler
2022	J	`jnl`	SymEx-VP: An open source virtual prototype for OS-agnostic concolic testing of IoT firmware. J. Syst. Archit. Sören Tempel, Vladimir Herdt, Rolf Drechsler
2022	C	`conf`	Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study. DSD Sallar Ahmadi-Pour, Sangeet Saha, Vladimir Herdt, Rolf Drechsler, Klaus D. McDonald-Maier
2022	J	`jnl`	The MicroRV32 framework: An accessible and configurable open source RISC-V cross-level platform for education and research. J. Syst. Archit. Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
2022	A	`conf`	The Scale4Edge RISC-V Ecosystem. DATE Wolfgang Ecker, Peer Adelt, Wolfgang Müller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, Gerhard Angst, Ralf Wimmer, Andreas Mauderer, Rafael Stahl, Karsten Emrich, Daniel Mueller-Gritschneder, Bernd Becker, Philipp Scholl, Eyck Jentzsch, Jan Schlamelcher, Kim Grüttner, Paul Palomero Bernardo, Oliver Bringmann, Mihaela Damian, Julian Oppermann, Andreas Koch, Jörg Bormann, Johannes Partzsch, Christian Mayr, Wolfgang Kunz
2022	J	`jnl`	Towards Quantification and Visualization of the Effects of Concretization During Concolic Testing. IEEE Embed. Syst. Lett. Sören Tempel, Vladimir Herdt, Rolf Drechsler
2022	C	`conf`	Unified HW/SW Coverage: A Novel Metric to Boost Coverage-guided Fuzzing for Virtual Prototype based HW/SW Co-Verification. FDL Niklas Bruns, Vladimir Herdt, Rolf Drechsler
2022	A*	`conf`	Verifying SystemC TLM peripherals using modern C++ symbolic execution tools. DAC Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
2022	C	`conf`	Virtual Prototype based Analysis of Neural Network Cache Behavior for Tiny Edge Device. FDL Alexander Fratzer, Vladimir Herdt, Christoph Lüth, Rolf Drechsler
2022	C	`conf`	Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions. DDECS Milan Funck, Vladimir Herdt, Rolf Drechsler
2021	J	`jnl`	Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform. J. Syst. Archit. Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler
2021	A	`conf`	An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes. DATE Sören Tempel, Vladimir Herdt, Rolf Drechsler
2021	—	`conf`	Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion. MBMV Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
2021	C	`conf`	In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes. FDL Sören Tempel, Vladimir Herdt, Rolf Drechsler
2021	C	`conf`	Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level. VLSI-SoC Frank Riese, Vladimir Herdt, Daniel Große, Rolf Drechsler
2021	—	`conf`	Mutation-based Compliance Testing for RISC-V. ASP-DAC Vladimir Herdt, Sören Tempel, Daniel Große, Rolf Drechsler
2021	C	`conf`	RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems. FDL Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
2021	J	`jnl`	Toward RISC-V CSR Compliance Testing. IEEE Embed. Syst. Lett. Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler
2021	A*	`conf`	Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing. DAC Sören Tempel, Vladimir Herdt, Rolf Drechsler
2021	A	`conf`	Vertical IP Protection of the Next-Generation Devices: Quo Vadis? DATE Shubham Rai, Siddharth Garg, Christian Pilato, Vladimir Herdt, Elmira Moussavi, Dominik Sisejkovic, Ramesh Karri, Rolf Drechsler, Farhad Merchant, Akash Kumar
2020	C	`conf`	Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime. ICCD Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler
2020	A*	`conf`	Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side DAC Vladimir Herdt, Daniel Große, Rolf Drechsler
2020	A*	`conf`	Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes. DAC Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
2020	C	`conf`	Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study. FDL Vladimir Herdt, Daniel Große, Eyck Jentzsch, Rolf Drechsler
2020	—	`conf`	Efficient Techniques to Strongly Enhance the Virtual Prototype Based Design Flow. ISVLSI Vladimir Herdt, Rolf Drechsler
2020	A	`conf`	Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes DATE Vladimir Herdt, Daniel Große, Rolf Drechsler
2020	J	`jnl`	RISC-V based virtual prototype: An extensible and configurable platform for the system-level. J. Syst. Archit. Vladimir Herdt, Daniel Große, Pascal Pieper, Rolf Drechsler
2020	B	`conf`	RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms. ATVA Vladimir Herdt, Daniel Große, Rolf Drechsler
2020	A	`conf`	Towards Specification and Testing of RISC-V ISA Compliance DATE Vladimir Herdt, Daniel Große, Rolf Drechsler
2020	—	`ch.`	Verbessertes Virtual Prototyping für den Entwurfsablauf. Ausgezeichnete Informatikdissertationen Vladimir Herdt
2020	—	`conf`	Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes. ACM Great Lakes Symposium on VLSI Vladimir Herdt, Daniel Große, Jonas Wloka, Tim Güneysu, Rolf Drechsler
2020	—	`conf`	Verifying Safety Properties of Robotic Plans Operating in Real-World Environments via Logic-Based Environment Modeling. ISoLA (3) Tim Meywerk, Marcel Walter, Vladimir Herdt, Jan Kleinekathöfer, Daniel Große, Rolf Drechsler
2019	J	`jnl`	Combining sequentialization-based verification of multi-threaded C programs with symbolic Partial Order Reduction. Int. J. Softw. Tools Technol. Transf. Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2019	A*	`conf`	Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study. DAC Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
2019	—	`—`	Efficient modeling, verification and analysis techniques to enhance the virtual prototype based design flow for embedded systems. Vladimir Herdt
2019	—	`conf`	Maximizing power state cross coverage in firmware-based power management. ASP-DAC Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2019	C	`conf`	Systematic RISC-V based Firmware Design FDL Vladimir Herdt, Daniel Große, Rolf Drechsler, Christoph Gerum, Alexander Louis-Ferdinand Jung, Joscha Benz, Oliver Bringmann, Michael Schwarz, Dominik Stoffel, Wolfgang Kunz
2019	C	`conf`	Towards Formal Verification of Plans for Cognition-Enabled Autonomous Robotic Agents. DSD Tim Meywerk, Marcel Walter, Vladimir Herdt, Daniel Große, Rolf Drechsler
2019	A	`conf`	Verifying Instruction Set Simulators using Coverage-guided Fuzzing DATE Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
2019	J	`jnl`	Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2018	C	`conf`	Extensible and Configurable RISC-V Based Virtual Prototype. FDL Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
2018	A	`conf`	Resilience evaluation via symbolic fault injection on intermediate code. DATE Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
2018	—	`conf`	Towards Automated Refinement of TLM Properties to RTL. MBMV Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2018	A	`conf`	Towards fully automated TLM-to-RTL property refinement. DATE Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2017	A	`conf`	Data flow testing for virtual prototypes. DATE Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, Rolf Drechsler
2017	A	`conf`	Early SoC security validation by VP-based static information flow analysis. ICCAD Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2017	—	`conf`	Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach. FDL (Selected Papers) Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2017	C	`conf`	Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach. FDL Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2016	A	`conf`	Compiled symbolic simulation for systemC. ICCAD Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2016	—	`book`	Complete Symbolic Simulation of SystemC Models - Efficient Formal Verification of Finite Non-Terminating Programs Vladimir Herdt
2016	C	`conf`	On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study. FDL Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2016	—	`conf`	ParCoSS: Efficient Parallelized Compiled Symbolic Simulation. CAV (2) Vladimir Herdt, Hoang Minh Le, Daniel Große, Rolf Drechsler
2016	A	`conf`	Towards formal verification of real-world SystemC TLM peripheral models - a case study. DATE Hoang Minh Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
2015	B	`conf`	Lazy-CSeq-SP: Boosting Sequentialization-Based Verification of Multi-threaded C Programs via Symbolic Pruning of Redundant Schedules. ATVA Vladimir Herdt, Hoang Minh Le, Daniel Große, Rolf Drechsler
2015	A*	`conf`	Verifying SystemC using stateful symbolic simulation. DAC Vladimir Herdt, Hoang Minh Le, Rolf Drechsler
2013	A*	`conf`	Verifying SystemC using an intermediate verification language and symbolic simulation. DAC Hoang Minh Le, Daniel Große, Vladimir Herdt, Rolf Drechsler