Vivekananda M. Vedula

14 papers A 2Misc 5Journal 3Unranked 4
YearRankTypeTitle / Venue / Authors
2011 — conf
A Unified Formal Framework for Analyzing Functional and Speed-path Properties.
MTV
Oswaldo Olivo, Sandip Ray, Jayanta Bhadra, Vivekananda M. Vedula
2008 J jnl
Automatic Constraint Based Test Generation for Behavioral HDL Models.
IEEE Trans. Very Large Scale Integr. Syst.
Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti, Vivekananda M. Vedula, K. S. Maneperambil
2007 — conf
A Scalable Symbolic Simulator for Verilog RTL.
MTV
Sasidhar Sunkari, Supratik Chakraborty, Vivekananda M. Vedula, Kailasnath Maneparambil
2007 J jnl
Controllability-Driven Peak Dynamic Power Estimation for VLSI Circuits.
J. Low Power Electron.
K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula
2007 Misc conf
Controllability-driven Power Virus Generation for Digital Circuits.
VLSI Design
K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula
2007 Misc conf
Power Virus Generation Using Behavioral Models of Circuits.
VTS
K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti, Vivekananda M. Vedula
2004 Misc conf
Program Slicing for ATPG-Based Property Checking.
VLSI Design
Vivekananda M. Vedula, Whitney J. Townsend, Jacob A. Abraham
2003 J jnl
A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages.
J. Electron. Test.
Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra, Raghuram S. Tupuri
2003 Misc conf
Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines.
VLSI Design
Daniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula
2002 A conf
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis.
DATE
Vivekananda M. Vedula, Jacob A. Abraham
2002 — conf
Native Mode Functional Self-Test Generation for Systems-on-Chip.
ISQED
Kamalnayan Jayaraman, Vivekananda M. Vedula, Jacob A. Abraham
2002 Misc conf
Program Slicing for Hierarchical Test Generation.
VTS
Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra
2002 A conf
Verifying Properties Using Sequential ATPG.
ITC
Jacob A. Abraham, Vivekananda M. Vedula, Daniel G. Saab
2000 — conf
A novel methodology for hierarchical test generation using functional constraint composition.
HLDVT
Vivekananda M. Vedula, Jacob A. Abraham