Viveka Konandur Rajanna

17 papers Journal 4Unranked 13
YearRankTypeTitle / Venue / Authors
2026 J jnl
SRAM Static Entropy Extraction From Every Single Transistor in Unmodified Bitcell and Data Fingerprinting for Provenance Assurance.
IEEE J. Solid State Circuits
Tianqi Wang, Joydeep Basu, Viveka Konandur Rajanna, Massimo Alioto
2024 — conf
122.7 TOPS/W Stdcell-Based DNN Accelerator Based on Transition Density Data Representation, Clock-Less MAC Operation, Pseudo-Sparsity Exploitation in 40 nm.
VLSI Technology and Circuits
Animesh Gupta, Japesh Vohra, Viveka Konandur Rajanna, Massimo Alioto
2024 — conf
SRAM Physically Unclonable Function Extracting Static Entropy from Every Bitcell Transistor for 6 bit/bitcell and Data Fingerprinting Capability for Provenance Assurance.
A-SSCC
Tianqi Wang, Joydeep Basu, Viveka Konandur Rajanna, Massimo Alioto
2023 — conf
ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm.
VLSI Technology and Circuits
Joydeep Basu, Sachin Taneja, Viveka Konandur Rajanna, Tianqi Wang, Massimo Alioto
2023 — conf
Energy-Efficient Computation in Constrained Systems with Machine Learning Workloads.
iSES
Viveka Konandur Rajanna
2023 — conf
Single-Antenna Backscattered BLE5 Transmitter with up to 97m Range, 10.6 μW Peak Power for Purely-Harvested Green Systems.
ESSCIRC
Karim Ali Ahmed, Ruiyuan Yang, Praveenakumar Shivappa Salamani, Viveka Konandur Rajanna, Massimo Alioto
2023 — conf
Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm.
VLSI Technology and Circuits
Animesh Gupta, Sayan Kumar, Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto
2022 — conf
DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm.
CICC
Animesh Gupta, Viveka Konandur Rajanna, Thoithoi Salam, Saurabh Jain, Orazio Aiello, Paolo Crovetti, Massimo Alioto
2022 — conf
Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis Attacks.
VLSI Technology and Circuits
Viveka Konandur Rajanna, Himadri Singh Raghav, Tianqi Wang, Massimo Alioto
2022 J jnl
In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security.
IEEE J. Solid State Circuits
Sachin Taneja, Viveka Konandur Rajanna, Massimo Alioto
2021 — conf
36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security.
ISSCC
Sachin Taneja, Viveka Konandur Rajanna, Massimo Alioto
2021 — conf
Fully-Digital Self-Calibrating Decoder with Sub-µW, 1.6fJ/convstep and 0.0075mm
VLSI Circuits
Prachi Agarwal, Viveka Konandur Rajanna, Toh Wei Da, Benjamin C. K. Tee, Massimo Alioto
2021 J jnl
On-Chip Links With Energy-Quality Tradeoff in Error-Resilient and Machine Learning Applications.
IEEE J. Solid State Circuits
Viveka Konandur Rajanna, Massimo Alioto
2021 — conf
SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm
ESSCIRC
Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto
2021 — conf
SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm
ESSDERC
Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto
2019 — conf
Low-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient Applications.
CICC
Viveka Konandur Rajanna, Massimo Alioto
2016 J jnl
A Variation-Tolerant Replica-Based Reference-Generation Technique for Single-Ended Sensing in Wide Voltage-Range SRAMs.
IEEE Trans. Very Large Scale Integr. Syst.
Viveka Konandur Rajanna, Bharadwaj Amrutur