Vivek K. De

22 papers Journal 19Unranked 3
YearRankTypeTitle / Venue / Authors
2022 — conf
An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOS.
ISSCC
Raghavan Kumar, Vikram B. Suresh, Mark A. Anders, Steven K. Hsu, Amit Agarwal, Vivek K. De, Sanu K. Mathew
2017 J jnl
A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS.
IEEE J. Solid State Circuits
Sudhir Satpathy, Sanu K. Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy, Vivek K. De
2015 J jnl
Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design.
ACM J. Emerg. Technol. Comput. Syst.
Vivek K. De, Andrew B. Kahng, Tanay Karnik, Bao Liu, Milad Maleki, Lu Wang
2013 J jnl
A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance.
IEEE J. Solid State Circuits
Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, James W. Tschanz
2013 J jnl
Adaptive and Resilient Circuits for Dynamic Variation Tolerance.
IEEE Des. Test
Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Tanay Karnik, Vivek K. De
2012 — conf
A 22nm dynamically adaptive clock distribution for voltage droop tolerance.
VLSIC
Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, Jim Tschanz
2011 J jnl
A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance.
IEEE J. Solid State Circuits
Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De
2011 J jnl
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling.
IEEE J. Solid State Circuits
Jason Howard, Saurabh Dighe, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar, Shailendra Jain, Vasantha Erraguntla, Michael Konow, Michael Riepen, Matthias Gries, Guido Droege, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek K. De, Rob F. Van der Wijngaart
2011 J jnl
All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control.
IEEE Trans. Circuits Syst. I Regul. Pap.
Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De
2011 J jnl
Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays.
IEEE J. Solid State Circuits
Arijit Raychowdhury, Bibiche M. Geuskens, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad M. Khellah, Vivek K. De
2011 J jnl
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor.
IEEE J. Solid State Circuits
Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek K. De, Shekhar Borkar
2009 J jnl
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology.
IEEE J. Solid State Circuits
Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi
2009 J jnl
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance.
IEEE J. Solid State Circuits
Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De
2008 J jnl
Accurate Estimation of SRAM Dynamic Stability.
IEEE Trans. Very Large Scale Integr. Syst.
D. E. Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek K. De
2008 — conf
Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance.
ISSCC
Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De
2008 J jnl
Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses.
IEEE Trans. Circuits Syst. I Regul. Pap.
Maged Ghoneima, Muhammad M. Khellah, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail, Vivek K. De
2004 J jnl
Low-voltage-swing monolithic dc-dc conversion.
IEEE Trans. Circuits Syst. II Express Briefs
Volkan Kursun, Siva G. Narendra, Vivek K. De, Eby G. Friedman
1998 J jnl
Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits.
IEEE Trans. Very Large Scale Integr. Syst.
P. Pant, Vivek K. De, A. Chatterjee
1994 J jnl
Short channel models and scaling limits of SOI and bulk MOSFETs.
IEEE J. Solid State Circuits
Bhavna Agrawal, Vivek K. De, Joseph M. Pimbley, James D. Meindl
1993 J jnl
An analytical threshold voltage and subthreshold current model for short-channel AlGaAs/GaAs MODFETs.
IEEE J. Solid State Circuits
Vivek K. De, James D. Meindl
1993 J jnl
An analytical threshold voltage and subthreshold current model for short-channel MESFETs.
IEEE J. Solid State Circuits
Vivek K. De, James D. Meindl
1993 J jnl
Analytical drain current models for AlGaAs/GaAs MODFET's including subthreshold conduction.
IEEE J. Solid State Circuits
Vivek K. De, James D. Meindl