Vivek Chickermane

50 papers A* 2A 20B 1C 1Misc 6Journal 8Unranked 12

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	Embedded Trace: A Key Enabler for Silicon Lifecycle Management. ITC Vivek Chickermane, Marcel Zak, Mat O'Donnell
2025	A	`conf`	Embedded Trace: A Key Enabler for Silicon Lifecycle Management. ITC Vivek Chickermane, Marcel Zak, Mat O'Donnell
2024	J	`jnl`	The Future of Design for Test and Silicon Lifecycle Management. IEEE Des. Test Janusz Rajski, Vivek Chickermane, Jean-François Côté, Stephan Eggersglüß, Nilanjan Mukherjee, Jerzy Tyszer
2022	A	`conf`	PPA Optimization of Test Points in Automotive Designs. ITC Brian Foutz, Sarthak Singhal, Prateek Kumar Rai, Krishna Chakravadhanula, Vivek Chickermane, Bharath Nandakumar, Sameer Chillarige, Christos Papameletis, Satish Ravichandran
2020	J	`jnl`	Guest Editors' Introduction: Selected Papers from IEEE VLSI Test Symposium. IEEE Des. Test Stefano Di Carlo, Peilin Song, Vivek Chickermane
2019	Misc	`conf`	Observation Point Placement for Improved Logic Diagnosis based on Large Sets of Candidate Faults. VTS Irith Pomeranz, Vivek Chickermane, Srikanth Venkataraman
2019	A	`conf`	Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications. ITC Christos Papameletis, Vivek Chickermane, Brian Foutz, Sarthak Singhal, Krishna Chakravadhanula
2017	A	`conf`	Advancing test compression to the physical dimension. ITC Krishna Chakravadhanula, Vivek Chickermane, Paul Cunningham, Brian Foutz, Dale Meehl, Louis Milano, Christos Papameletis, David Scott, Steev Wilcox
2015	J	`jnl`	A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers. IEEE Des. Test Christos Papameletis, Brion L. Keller, Vivek Chickermane, Said Hamdioui, Erik Jan Marinissen
2015	—	`conf`	A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures. NATW Sameer Chillarige, S. Virdi, Anil Malik, Krishna Chakravadhanula, Vivek Chickermane, Joe Swenton, G. Vandling
2015	—	`conf`	At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic. ATS Konstantin Shibin, Vivek Chickermane, Brion L. Keller, Christos Papameletis, Erik Jan Marinissen
2014	A	`conf`	Efficient testing of hierarchical core-based SOCs. ITC Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen
2014	Misc	`conf`	Innovative practices session 1C: Existing/emerging low power techniques. VTS Charutosh Dixit, Ramesh C. Tekumalla, Wei Zhao, Nilanjan Mukherjee, Vivek Chickermane
2014	Misc	`conf`	Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices. VLSID Srivaths Ravi, Vivek Chickermane, Krishna Chakravadhanula
2013	B	`conf`	Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers. ETS Christos Papameletis, Brion L. Keller, Vivek Chickermane, Erik Jan Marinissen, Said Hamdioui
2013	A	`conf`	SmartScan - Hierarchical test compression for pin-limited low power designs. ITC Krishna Chakravadhanula, Vivek Chickermane, Don Pearl, Akhil Garg, R. Khurana, Subhasish Mukherjee, P. Nagaraj
2013	A	`conf`	Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. ITC Sandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim
2012	A	`conf`	DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. ITC Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen
2011	—	`conf`	Automation of 3D-DfT Insertion. Asian Test Symposium Sergej Deutsch, Vivek Chickermane, Brion L. Keller, Subhasish Mukherjee, Mario Konijnenburg, Erik Jan Marinissen, Sandeep Kumar Goel
2010	A	`conf`	Low cost at-speed testing using On-Product Clock Generation compatible with test compression. ITC Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise
2009	J	`jnl`	Automating IEEE 1500 Core Test—An EDA Perspective. IEEE Des. Test Comput. Krishna Chakravadhanula, Vivek Chickermane
2009	A	`conf`	Capture power reduction using clock gating aware test generation. ITC Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Prashant Narang
2009	—	`conf`	Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?. Asian Test Symposium Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Anis Uzzaman
2008	A	`conf`	A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs. ITC Vivek Chickermane, Patrick R. Gallagher Jr., James Sage, Paul Yuan, Krishna Chakravadhanula
2008	—	`conf`	Test Generation for State Retention Logic. ATS Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Steven Gregor
2007	—	`conf`	Low Power Reduced Pin Count Test Methodology. ATS Krishna Chakravadhanula, Nitin Parimi, Brian Foutz, Bing Li, Vivek Chickermane
2006	—	`conf`	A Scalable Architecture for On-Chip Compression: Options and Trade-Offs. ATS Anis Uzzaman, Brion L. Keller, Vivek Chickermane
2006	—	`conf`	Automation of IEEE 1149.6 Boundary Scan Synthesis in an ASIC Methodology. ATS Brian Foutz, Vivek Chickermane, Bing Li, Harry Linzer, Gary Kunselman
2006	—	`conf`	Early Life Cycle Yield Learning for Nanometer Devices Using Volume Yield Diagnostics Analysis. ATS Sanae Seike, Ken Namura, Yukio Ohya, Anis Uzzaman, Shinichi Arima, Dale Meehl, Vivek Chickermane, Azumi Kobayashi, Satoshi Tanaka, Hiroyuki Adachi
2005	—	`conf`	Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. Asian Test Symposium Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi
2005	—	`conf`	Practical Aspects of Delay Testing for Nanometer Chips. Asian Test Symposium Vivek Chickermane, Brion L. Keller, Kevin McCauley, Anis Uzzaman
2004	A	`conf`	An Economic Analysis and ROI Model for Nanometer Test. ITC Brion L. Keller, Mick Tegethoff, Thomas Bartenstein, Vivek Chickermane
2004	A	`conf`	Channel Masking Synthesis for Efficient On-Chip Test Compression. ITC Vivek Chickermane, Brian Foutz, Brion L. Keller
2001	A	`conf`	A building block BIST methodology for SOC designs: a case study. ITC Patrick R. Gallagher Jr., Vivek Chickermane, Steven Gregor, Thomas S. Pierre
2001	J	`jnl`	System-on-Chip Testability Using LSSD Scan Structures. IEEE Des. Test Comput. Kamran Zarrineh, Shambhu J. Upadhyaya, Vivek Chickermane
2000	Misc	`conf`	Integrating Logic BIST in VLSI Designs with Embedded Memories. VTS Vivek Chickermane, Scott Richter, Carl Barnhart
1997	A	`conf`	Addressing Early Design-For-Test Synthesis in a Production Environment. ITC Vivek Chickermane, Kamran Zarrineh
1996	C	`conf`	A Design For Test Perspective on I/O Management. ICCD Kamran Zarrineh, Vivek Chickermane, Gareth Nicholls, Mike Palmer
1995	J	`jnl`	Sequential circuit testability enhancement using a nonscan approach. IEEE Trans. Very Large Scale Integr. Syst. Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel
1994	J	`jnl`	Addressing design for testability at the architectural level. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vivek Chickermane, Jaushin Lee, Janak H. Patel
1994	J	`jnl`	An observability enhancement approach for improved testability and at-speed test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel
1993	Misc	`conf`	Impact of high level functional constraints on testability. VTS Jaushin Lee, Vivek Chickermane, Janak H. Patel
1993	A*	`conf`	Non-Scan Design-for-Testability Techniques for Sequential Circuits. DAC Vivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, Janak H. Patel
1992	A	`conf`	A comparative study of design for testability methods using high-level and gate-level descriptions. ICCAD Vivek Chickermane, Jaushin Lee, Janak H. Patel
1992	A*	`conf`	APT: An Area-Performance-Testability Driven Placement Algorithm. DAC Sungho Kim, Prithviraj Banerjee, Vivek Chickermane, Janak H. Patel
1992	A	`conf`	Design for Testability Using Architectural Descriptions. ITC Vivek Chickermane, Jaushin Lee, Janak H. Patel
1992	Misc	`conf`	Probe point insertion for at-speed test. VTS Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel
1991	A	`conf`	A Fault Oriented Partial Scan Design Approach. ICCAD Vivek Chickermane, Janak H. Patel
1991	—	`conf`	Restructuring VLSI layout representations for efficiency. EURO-DAC Ravi Nair, Vivek Chickermane, Ray Chamberlain
1990	A	`conf`	An optimization based approach to the partial scan design problem. ITC Vivek Chickermane, Janak H. Patel