Vittoriano Muttillo

43 papers A* 1A 1B 3C 6Journal 15Unranked 16
YearRankTypeTitle / Venue / Authors
2026 J jnl
Empowering Retail Visitors Through Edge AI: A User-Centered Case Study of Cooperative Totem Systems.
IEEE Access
Gianluca Brilli, Federica Caruso, Giacomo Valente, Alberto Carlevaro, Chiara Garibotto, Jacopo Motta, Vittoriano Muttillo, Damiano Vallocchia, Paolo Burgio
2026 J jnl
Experiences and challenges from a software ecosystem for cyber-physical systems development: An empirical study on industry-academia collaboration.
J. Syst. Softw.
Vittoriano Muttillo, Romina Eramo, Johan Cederbladh, Per Erik Strandberg, Adnan Ashraf
2025 J jnl
A New HW/SW Co-Design Approach for Monitored Systems-on-Chip Development.
ACM Trans. Embed. Comput. Syst.
Giacomo Valente, Vittoriano Muttillo, Luigi Pomante, Daniele Frigioni, Tania Di Mascio
2025 — conf
Coupling LLMs and Model-Driven Engineering to Support Synthetic Generation of BPMN Artifacts.
MODELS-C
Vittoriano Muttillo, Romina Eramo, Riccardo Rubei, Luca Berardinelli
2025 J jnl
Leveraging synthetic trace generation of modeling operations for intelligent modeling assistants using large language models.
Inf. Softw. Technol.
Vittoriano Muttillo, Claudio Di Sipio, Riccardo Rubei, Luca Berardinelli
2025 J jnl
Leveraging traffic injection and quality-of-service to control the reconfiguration delay.
J. Syst. Archit.
Giacomo Valente, Vittoriano Muttillo, Fabio Federici, Luigi Pomante, Tania Di Mascio
2025 A conf
Multi-Partner Project: A Model-Driven Engineering Framework for Federated Digital Twins of Industrial Systems (MATISSE).
DATE
Alessio Bucaioni, Romina Eramo, Luca Berardinelli, Hugo Bruneliere, Benoît Combemale, Djamel Eddine Khelladi, Vittoriano Muttillo, Andrey Sadovykh, Manuel Wimmer
2025 — conf
System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric.
PARMA-DITAM
Vittoriano Muttillo, Vincenzo Stoico, Giacomo Valente, Marco Santic, Luigi Pomante, Daniele Frigioni
2024 J jnl
Analysis of Reconfiguration Delay in Heterogeneous Systems-on-Chip via Traffic Injection.
IEEE Embed. Syst. Lett.
Giacomo Valente, Vittoriano Muttillo, Fabio Federici, Luigi Pomante, Tania Di Mascio
2024 J jnl
Experiences and challenges from developing cyber-physical systems in industry-academia collaboration.
Softw. Pract. Exp.
Johan Cederbladh, Romina Eramo, Vittoriano Muttillo, Per Erik Strandberg
2024 C conf
SLIDE-x-ML: System-Level Infrastructure for Dataset E-xtraction and Machine Learning Framework for High-Level Synthesis Estimations.
ICCD
Vittoriano Muttillo, Vincenzo Stoico, Marco Santic, Giacomo Valente, Luigi Pomante, Daniele Frigioni
2024 A* conf
Towards Synthetic Trace Generation of Modeling Operations using In-Context Learning Approach.
ASE
Vittoriano Muttillo, Claudio Di Sipio, Riccardo Rubei, Luca Berardinelli, MohammadHadi Dehghani
2024 J jnl
Towards Synthetic Trace Generation of Modeling Operations using In-Context Learning Approach.
CoRR
Vittoriano Muttillo, Claudio Di Sipio, Riccardo Rubei, Luca Berardinelli, MohammadHadi Dehghani
2023 J jnl
SystemC-based Co-Simulation/Analysis for System-Level Hardware/Software Co-Design.
Comput. Electr. Eng.
Vittoriano Muttillo, Luigi Pomante, Marco Santic, Giacomo Valente
2022 J jnl
AIDOaRt: AI-augmented Automation for DevOps, a model-based framework for continuous development in Cyber-Physical Systems.
Microprocess. Microsystems
Hugo Bruneliere, Vittoriano Muttillo, Romina Eramo, Luca Berardinelli, Abel Gómez, Alessandra Bagnato, Andrey Sadovykh, Antonio Cicchetti
2021 C conf
AIDOaRt: AI-augmented Automation for DevOps, a Model-based Framework for Continuous Development in Cyber-Physical Systems.
DSD
Romina Eramo, Vittoriano Muttillo, Luca Berardinelli, Hugo Bruneliere, Abel Gómez, Alessandra Bagnato, Andrey Sadovykh, Antonio Cicchetti
2021 — conf
Model-Based HW/SW Co-Design Methodology for UAV Systems Development.
MECO
Vittoriano Muttillo, Vincenzo Stoico
2021 B conf
Statement-Level Timing Estimation for Embedded System Design Using Machine Learning Techniques.
ICPE
Vittoriano Muttillo, Paolo Giammatteo, Vincenzo Stoico
2020 — conf
A Low Cost and Flexible Power Line Communication Sensory System for Home Automation.
MetroInd4.0&IoT
Mirco Muttillo, Vittoriano Muttillo, Luigi Pomante, Leonardo Pantoli
2020 — conf
An OpenMP Parallel Genetic Algorithm for Design Space Exploration of Heterogeneous Multi-processor Embedded Systems.
PARMA-DITAM@HiPEAC
Vittoriano Muttillo, Paolo Giammatteo, Giuseppe Fiorilli, Luigi Pomante
2020 J jnl
An early-stage statement-level metric for energy characterization of embedded processors.
Microprocess. Microsystems
Vittoriano Muttillo, Paolo Giammatteo, Vincenzo Stoico, Luigi Pomante
2020 C conf
Run-time Monitoring and Trace Analysis Methodology for Component-based Embedded Systems Design Flow.
DSD
Vittoriano Muttillo, Giacomo Valente, Luigi Pomante, Hector Posadas, Javier Merino, Eugenio Villar
2020 — conf
Towards the Design of Microcontroller Based Embedded Sensory systems with a Five-Parameter Single Diode Estimation Method for Photovoltaic Panels.
MetroInd4.0&IoT
Mirco Muttillo, Vittoriano Muttillo, Tullio de Rubeis
2019 J jnl
Benchmarking Analysis and Characterization of Hypervisors for Space Multicore Systems.
J. Aerosp. Inf. Syst.
Vittoriano Muttillo, Luca Tiberi, Luigi Pomante, Paolo Serri
2019 C conf
HW/SW Co-Design Framework for Mixed-Criticality Embedded Systems Considering Xtratum-Based SW Partitions.
DSD
Vittoriano Muttillo, Luigi Pomante, Patricia Balbastre, José E. Simó, Alfons Crespo
2019 — —
HW/SW co-design methodology and framework for mixed-criticality and real-time embedded systems.
Vittoriano Muttillo
2019 — conf
J4CS: An Early-Stage Statement-Level Metric for Energy Consumption of Embedded SW.
MECO
Vittoriano Muttillo
2019 J jnl
The AQUAS ECSEL Project Aggregated Quality Assurance for Systems: Co-Engineering Inside and Across the Product Life Cycle.
Microprocess. Microsystems
Luigi Pomante, Vittoriano Muttillo, Bohuslav Krena, Tomás Vojnar, Filip Veljkovic, Pacome Magnin, Martin Matschnig, Bernhard Fischer, Jabier Martinez, Thomas Gruber
2018 — conf
CC4CS: an Off-the-Shelf Unifying Statement-Level Performance Metric for HW/SW Technologies.
ICPE Companion
Vittoriano Muttillo, Giacomo Valente, Luigi Pomante, Vincenzo Stoico, Fausto D'Antonio, Fabio Salice
2018 — conf
Criticality-aware Design Space Exploration for Mixed-Criticality Embedded Systems.
ICPE Companion
Vittoriano Muttillo, Giacomo Valente, Luigi Pomante
2018 — conf
Criticality-driven Design Space Exploration for Mixed-Criticality Heterogeneous Parallel Embedded Systems.
PARMA-DITAM@HiPEAC
Vittoriano Muttillo, Giacomo Valente, Luigi Pomante
2018 C conf
Design Space Exploration for Mixed-Criticality Embedded Systems Considering Hypervisor-Based SW Partitions.
DSD
Vittoriano Muttillo, Giacomo Valente, Luigi Pomante
2018 — conf
HEPSIM: An ESL HW/SW co-simulator/analysis tool for heterogeneous parallel embedded systems.
MECO
Daniele Ciambrone, Vittoriano Muttillo, Luigi Pomante, Giacomo Valente
2018 — conf
HEPSYCODE-RT: a Real-Time Extension for an ESL HW/SW Co-Design Methodology.
RAPIDO
Vittoriano Muttillo, Giacomo Valente, Daniele Ciambrone, Vincenzo Stoico, Luigi Pomante
2018 — conf
Injecting hypervisor-based software partitions into Design Space Exploration activities considering mixed-criticality requirements.
MECO
Vittoriano Muttillo, Giacomo Valente
2017 B conf
An Efficient Performance-Driven Approach for HW/SW Co-Design.
ICPE
Daniele Di Pompeo, Emilio Incerto, Vittoriano Muttillo, Luigi Pomante, Giacomo Valente
2017 — conf
Simulation-Based Analysis of a Hardware Mechanism to Support Isolation in Mixed-Criticality Network on Chip.
EMS
Fabio Federici, Mattia Micozzi, Vittoriano Muttillo, Luigi Pomante, Giacomo Valente
2017 B conf
Time Bands: A Software Approach for Timing Analysis on Resource Constrained Systems.
ICPE
Giacomo Valente, Marco Rotondi, Vittoriano Muttillo
2016 C conf
A Flexible Profiling Sub-System for Reconfigurable Logic Architectures.
PDP
Giacomo Valente, Vittoriano Muttillo, Luigi Pomante, Fabio Federici, Marco Faccio, Andrea Moro, Serenella Ferri, Carlo Tieri
2016 J jnl
A design methodology for soft-core platforms on FPGA with SMP Linux, OpenMP support, and distributed hardware profiling system.
EURASIP J. Embed. Syst.
Vittoriano Muttillo, Giacomo Valente, Fabio Federici, Luigi Pomante, Marco Faccio, Carlo Tieri, Serenella Ferri
2016 — conf
Design and validation of multi-core embedded systems under time-to-prototype and high performance constraints.
RTSI
Marco Faccio, Fabio Federici, Giuseppe Marini, Vittoriano Muttillo, Luigi Pomante, Giacomo Valente
2015 — conf
Hardware performance sniffers for embedded systems profiling.
WISES
Andrea Moro, Fabio Federici, Giacomo Valente, Luigi Pomante, Marco Faccio, Vittoriano Muttillo
2014 J jnl
A Proposal to Expand the Community of Users Able to Process Historical Rainfall Data by Means of the Today Available Open Source Libraries.
J. Comput. Inf. Technol.
Paolino Di Felice, Luca Finocchio, Daniele Leombruni, Vittoriano Muttillo