Vita Pi-Ho Hu

30 papers A 3C 10Journal 6Unranked 11
YearRankTypeTitle / Venue / Authors
2025 C conf
Design Technology Co-Optimization for CFET SRAM Cells Considering Double-Sided Signal/Power Routing.
ISCAS
Yu-Cheng Lu, Meng-Lin Wu, Vita Pi-Ho Hu
2025 — conf
Uncertainty-Aware LiDAR-Camera Autonomy via Conformal Prediction and Principled Abstention.
COINS
Divake Kumar, Sina Tayebati, Nastaran Darabi, Vita Pi-Ho Hu, Amit Ranjan Trivedi
2024 C conf
Improved RF Performance with Buried Power Rail and Contact over Active Gate in Nanosheet FETs.
ISCAS
Hao-Chi Chiu, Vita Pi-Ho Hu
2023 — conf
Energy-Efficient SRAM with Emerging Technologies.
ICICDT
Vita Pi-Ho Hu
2021 C conf
Monolithic 3D SRAM Cell with Stacked Two-Dimensional Materials Based FETs at 2nm Node.
ISCAS
Vita Pi-Ho Hu, Cheng-Wei Su, Chun-Chi Yu, Chang-Ju Liu, Cheng-Yang Weng
2020 C conf
Improved Energy Efficiency for Ferroelectric FET Non-Volatile Memory using Split-Gate Design.
ISCAS
Yen-Wei Lee, Vita Pi-Ho Hu
2019 — conf
Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET.
ISQED
Hung-Han Lin, Vita Pi-Ho Hu
2019 C conf
Improved Read Stability and Writability of Negative Capacitance FinFET SRAM Cell for Subthreshold Operation.
ISCAS
Zhe-An Zheng, Vita Pi-Ho Hu
2016 C conf
Investigation of BTI reliability for monolithic 3D 6T SRAM with ultra-thin-body GeOI MOSFETs.
ISCAS
Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2015 — conf
Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices.
ICICDT
Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2015 C conf
Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness.
ISCAS
Chien-Ju Chen, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2015 — conf
Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications.
SoCC
Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2015 C conf
Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells.
ISCAS
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
2014 C conf
Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cells.
ISCAS
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
2014 J jnl
Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2014 J jnl
Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2014 C conf
Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling.
ISCAS
Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang
2014 J jnl
Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits.
Microelectron. Reliab.
Ming-Long Fan, Shao-Yu Yang, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang
2014 A conf
Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell.
ISLPED
Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2013 — conf
Device design and analysis of logic circuits and SRAMs for Germanium FinFETs on SOI and bulk substrates.
ISQED
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
2013 — conf
Impacts of single trap induced random telegraph noise on Si and Ge nanowire FETs, 6T SRAM cells and logic circuits.
ICICDT
Shao-Yu Yang, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2012 — conf
A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance.
ESSDERC
Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Ming-Fu Tsai, Chia-Hao Pao, Pin Su, Ching-Te Chuang
2012 — conf
A comprehensive comparative analysis of FinFET and Trigate device, SRAM and logic circuits.
APCCAS
Chia-Hao Pao, Ming-Long Fan, Ming-Fu Tsai, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2012 — conf
Impacts of random telegraph noise on the analog properties of FinFET and trigate devices and Widlar current source.
ICICDT
Chia-Hao Pao, Ming-Long Fan, Ming-Fu Tsai, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2012 J jnl
Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs.
IEEE Trans. Very Large Scale Integr. Syst.
Chien-Yu Hsieh, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2012 — conf
Stability and performance optimization of InGaAs-OI and GeOI hetero-channel SRAM cells.
ESSDERC
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
2012 J jnl
Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang
2011 J jnl
Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
2011 A conf
Analysis of power-performance for ultra-thin-body GeOI logic circuits.
ISLPED
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
2009 A conf
Design and analysis of ultra-thin-body SOI based subthreshold SRAM.
ISLPED
Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su, Ching-Te Chuang