Visvesh Sathe

25 papers A* 1A 3Journal 7Unranked 14
YearRankTypeTitle / Venue / Authors
2025 — conf
8.7 A Dual VDD-Temperature Sensor Employing Sensor Fusion with 2.4°C, 9mV (±3σ) Inaccuracy in 65nm CMOS.
ISSCC
Hikmet Seha Öztürk, Julian Arenas, Carlos Tokunaga, Nasser A. Kurd, Visvesh Sathe
2025 — conf
A 50-kHz BW 92.1-dB SNDR Incremental ADC Using a Back-End Sampling Two-Step NS-SAR Architecture with Concurrent Gain-Error + Noise Suppression.
CICC
Tzu-Han Wang, Chenyang Li, Dong Suk Kang, Ken Li, Xitie Zhang, Wei-En Lee, Visvesh Sathe, Shaolan Li
2025 — conf
A 95.9-dB SNDR 10-kHz BW 3rd-Order VCO-Based CT ΔΣ Modulator Using a Phase-Time Two-Step Quantizer.
CICC
Ken Li, Wei-En Lee, Xitie Zhang, Tian Xie, Tzu-Han Wang, Visvesh Sathe, Shaolan Li
2025 — conf
A Dynamically Reconfigurable Digital-Integrated Voltage-Regulator Fabric for Energy-Efficient DVFS in Multi-Domain soCs.
ISSCC
Julian Arenas, Chi-Hsiang Huang, Kevin Patino-Sosa, Jung-Jin Park, Hikmet Seha Öztürk, Visvesh Sathe
2022 — conf
A Reconfigurable Digital Beamforming V-Band Phased-Array Receiver.
ESSCIRC
Deniz Dosluoglu, Kun-Da Chu, Diego Peña-Colaiocco, Ivan Zhao, Visvesh Sathe, Jacques C. Rudell
2022 — conf
An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS.
RFID
James D. Rosenthal, Arindam Mandal, Visvesh Sathe, Matthew S. Reynolds
2022 A* conf
CANDLES: Channel-Aware Novel Dataflow-Microarchitecture Co-Design for Low Energy Sparse Neural Network Acceleration.
HPCA
Sumanth Gudaparthi, Sarabjeet Singh, Surya Narayanan, Rajeev Balasubramonian, Visvesh Sathe
2021 — conf
A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS.
ISSCC
Chi-Hsiang Huang, Xun Sun, Yidong Chen, Rajesh Pamula, Arindam Mandal, Visvesh Sathe
2020 J jnl
A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique.
IEEE J. Solid State Circuits
Yi Shen, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Xin Xin, Shubin Liu, Zhangming Zhu, Visvesh Sathe, Nan Sun
2020 J jnl
A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS.
IEEE J. Solid State Circuits
John P. Uehlin, William Anthony Smith, Venkata Rajesh Pamula, Eric P. Pepin, Steve I. Perlmutter, Visvesh Sathe, Jacques Christophe Rudell
2019 — conf
A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS.
ISSCC
Xun Sun, Akshat Boora, Wenbing Zhang, Venkata Rajesh Pamula, Visvesh Sathe
2019 J jnl
A 1-2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation.
IEEE J. Solid State Circuits
Fahim ur Rahman, Greg Taylor, Visvesh Sathe
2019 — conf
A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique.
CICC
Xiyuan Tang, Yi Shen, Linxiao Shen, Wenda Zhao, Zhangming Zhu, Visvesh Sathe, Nan Sun
2019 — conf
A Bidirectional Brain Computer Interface with 64-Channel Recording, Resonant Stimulation and Artifact Suppression in Standard 65nm CMOS.
ESSCIRC
John P. Uehlin, William Anthony Smith, Venkata Rajesh Pamula, Steve I. Perlmutter, Visvesh Sathe, Jacques Christophe Rudell
2019 J jnl
Bandwidth Extension on Raw Audio via Generative Adversarial Networks.
CoRR
Sung Kim, Visvesh Sathe
2019 — conf
Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS.
ISSCC
Fahim ur Rahman, Rajesh Pamula, Akshat Boora, Xun Sun, Visvesh Sathe
2018 A conf
MATIC: Learning around errors for efficient low-voltage neural network accelerators.
DATE
Sung Kim, Patrick Howe, Thierry Moreau, Armin Alaghi, Luis Ceze, Visvesh Sathe
2018 J jnl
Quasi-Resonant Clocking: Continuous Voltage-Frequency Scalable Resonant Clocking System for Dynamic Voltage-Frequency Scaling Systems.
IEEE J. Solid State Circuits
Fahim U. Rahman, Visvesh Sathe
2017 J jnl
Energy-Efficient Hybrid Stochastic-Binary Neural Networks for Near-Sensor Computing.
CoRR
Vincent T. Lee, Armin Alaghi, John P. Hayes, Visvesh Sathe, Luis Ceze
2017 A conf
Energy-efficient hybrid stochastic-binary neural networks for near-sensor computing.
DATE
Vincent T. Lee, Armin Alaghi, John P. Hayes, Visvesh Sathe, Luis Ceze
2017 J jnl
Exploring Computation-Communication Tradeoffs in Camera Systems.
CoRR
Amrita Mazumdar, Thierry Moreau, Sung Kim, Meghan Cowan, Armin Alaghi, Luis Ceze, Mark Oskin, Visvesh Sathe
2017 — conf
Exploring computation-communication tradeoffs in camera systems.
IISWC
Amrita Mazumdar, Thierry Moreau, Sung Kim, Meghan Cowan, Armin Alaghi, Luis Ceze, Mark Oskin, Visvesh Sathe
2016 A conf
Regenerative Breaking: Recovering Stored Energy from Inactive Voltage Domains for Energy-efficient Systems-on-Chip.
ISLPED
Ali Najafi, Jacques Christophe Rudell, Visvesh Sathe
2016 — conf
Tutorial 4A: Supply voltage noise and mitigation for real world SoCs.
SoCC
Visvesh Sathe, Andrew Marshall
2016 — conf
UVFR: A Unified Voltage and Frequency Regulator with 500MHz/0.84V to 100KHz/0.27V operating range, 99.4% current efficiency and 27% supply guardband reduction.
ESSCIRC
Samantak Gangopadhyay, Saad Bin Nasir, A. Subramanian, Visvesh Sathe, Arijit Raychowdhury