Visvesh S. Sathe

51 papers A 7Journal 21Unranked 23

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 32-Channel 85.4 dB SNDR Time-Multiplexed Neural Recording Front-End Achieving Within-Conversion Artifact Recovery. IEEE J. Solid State Circuits Arindam Mandal, Chi-Hsiang Huang, Julian Arenas, Wei-En Lee, Kevin Patino-Sosa, Philip Anschutz, Amanda L. Jacob, Keshav Ramachandra, Samuel J. Sober, Muhannad S. Bakir, Shaolan Li, Visvesh S. Sathe
2026	J	`jnl`	A 92.1-dB SNDR Easy-Driving Two-Step NS-SAR-Based Incremental ADC With Concurrent Gain-Error Plus Noise Suppression. IEEE J. Solid State Circuits Chenyang Li, Tzu-Han Wang, Dong Suk Kang, Ken Li, Xitie Zhang, Wei-En Lee, Visvesh S. Sathe, Shaolan Li
2026	J	`jnl`	A 95.9-dB SNDR 10-kHz BW Third-Order VCO-Based CT ΔΣ Modulator Using a Phase-Time Two-Step Quantizer. IEEE J. Solid State Circuits Ken Li, Wei-En Lee, Xitie Zhang, Tian Xie, Tzu-Han Wang, Visvesh S. Sathe, Shaolan Li
2026	J	`jnl`	A Compact, Highly-Digital Sensor-Fusion-Based Joint V IEEE J. Solid State Circuits Hikmet Seha Öztürk, Julian Arenas, Carlos Tokunaga, Nasser A. Kurd, Visvesh S. Sathe
2025	—	`conf`	A 0.14µJ Per-Acquisition Frequency Domain GPS Correlator Using Adaptive Compressive Sampling. CICC Jung-Jin Park, Julian Arenas, Kevin Patino-Sosa, Visvesh S. Sathe
2025	—	`conf`	A 32-Channel 85.4dB SNDR Time-multiplexed Neural Recording Frontend Achieving Within-Conversion Artifact Recovery. CICC Arindam Mandal, Chi-Hsiang Huang, Julian Arenas, Wei-En Lee, Philip Anschutz, Amanda L. Jacob, Keshav Ramachandra, Samuel J. Sober, Muhannad S. Bakir, Shaolan Li, Visvesh S. Sathe
2025	J	`jnl`	Computational Vector Stimulation for Spatially Targeted, Low-Latency Adaptive Neuromodulation With Common-Mode Artifact Suppression. IEEE Trans. Circuits Syst. I Regul. Pap. Arindam Mandal, Diego Peña-Colaiocco, Venkata Rajesh Pamula, Steve I. Perlmutter, Forrest Pape, Jacques C. Rudell, Visvesh S. Sathe
2024	J	`jnl`	Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits Mike Shuo-Wei Chen, Visvesh S. Sathe, Massimo Alioto, Jae-sun Seo, Hidehiro Shiga
2023	J	`jnl`	Regenerative Breaking: Optimal Energy Recycling for Energy Minimization in Duty-Cycled Domains. IEEE J. Solid State Circuits Chi-Hsiang Huang, Arindam Mandal, Diego Peña-Colaiocco, Edevaldo Pereira Da Silva, Visvesh S. Sathe
2022	—	`conf`	An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOS. ISSCC Diego Peña-Colaiocco, Chi-Hsiang Huang, Kun-Da Chu, Jacques Christophe Rudell, Visvesh S. Sathe
2022	—	`conf`	Energy Minimization of Duty-Cycled Systems Through Optimal Stored-Energy Recycling from Idle Domains. ISSCC Chi-Hsiang Huang, Arindam Mandal, Diego Peña-Colaiocco, Edevaldo Pereira Da Silva, Visvesh S. Sathe
2022	J	`jnl`	Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control. IEEE J. Solid State Circuits Chi-Hsiang Huang, Yidong Chen, Xun Sun, Arindam Mandal, Venkata Rajesh Pamula, Nasser A. Kurd, Visvesh S. Sathe
2021	—	`conf`	A 46-channel Vector Stimulator with 50mV Worst-Case Common-Mode Artifact for Low-Latency Adaptive Closed-Loop Neuromodulation. CICC Arindam Mandal, Diego Peña, Rajesh Pamula, Karam Khateeb, Logan Murphy, Azadeh Yazdan-Shahmorad, Steve I. Perlmutter, Forrest Pape, Jacques Christophe Rudell, Visvesh S. Sathe
2020	J	`jnl`	A 0.0023 mm IEEE Trans. Biomed. Circuits Syst. John P. Uehlin, William Anthony Smith, Venkata Rajesh Pamula, Steve I. Perlmutter, Jacques Christophe Rudell, Visvesh S. Sathe
2020	J	`jnl`	Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS. IEEE J. Solid State Circuits Fahim ur Rahman, Rajesh Pamula, Visvesh S. Sathe
2020	—	`conf`	Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS. VLSI Circuits Xun Sun, Akshat Boora, Rajesh Pamula, Chi-Hsiang Huang, Diego Peña-Colaiocco, Visvesh S. Sathe
2020	—	`conf`	UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS. VLSI Circuits Xun Sun, Akshat Boora, Rajesh Pamula, Chi-Hsiang Huang, Diego Peña-Colaiocco, Visvesh S. Sathe
2019	J	`jnl`	A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains. IEEE J. Solid State Circuits Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe
2019	J	`jnl`	An All-Digital Fused PLL-Buck Architecture for 82% Average V IEEE J. Solid State Circuits Xun Sun, Fahim ur Rahman, Venkata Rajesh Pamula, Sung Kim, Xi Li, Naveen John, Visvesh S. Sathe
2018	—	`conf`	A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor. ISSCC Xun Sun, Sung Kim, Fahim ur Rahman, Venkata Rajesh Pamula, Xi Li, Naveen John, Visvesh S. Sathe
2018	—	`conf`	An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS. VLSI Circuits Rajesh Pamula, Xun Sun, Sung Kim, Fahim ur Rahman, Baosen Zhang, Visvesh S. Sathe
2018	—	`conf`	An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor. VLSI Circuits Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe
2018	J	`jnl`	Architecture Considerations for Stochastic Computing Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vincent T. Lee, Armin Alaghi, Rajesh Pamula, Visvesh S. Sathe, Luis Ceze, Mark Oskin
2018	J	`jnl`	Energy-Efficient Neural Network Acceleration in the Presence of Bit-Level Memory Errors. IEEE Trans. Circuits Syst. I Regul. Pap. Sung Kim, Patrick Howe, Thierry Moreau, Armin Alaghi, Luis Ceze, Visvesh S. Sathe
2016	—	`conf`	19.6 voltage-scalable frequency-independent quasi-resonant clocking implementation of a 0.7-to-1.2V DVFS System. ISSCC Fahim U. Rahman, Visvesh S. Sathe
2016	A	`conf`	All-digital hybrid-control buck converter for Integrated Voltage Regulator applications. DATE Ta-Tung Yen, Bin Yu, Visvesh S. Sathe
2016	J	`jnl`	Exploiting Electrocorticographic Spectral Characteristics for Optimized Signal Chain Design: A 1.08 Analog Front End With Reduced ADC Resolution Requirements. IEEE Trans. Biomed. Circuits Syst. William Anthony Smith, Brian Mogen, Eberhard E. Fetz, Visvesh S. Sathe, Brian P. Otis
2016	J	`jnl`	Introduction to the Special Section on the 2015 Custom Integrated Circuits Conference. IEEE J. Solid State Circuits Patrick Chiang, Visvesh S. Sathe
2015	A	`conf`	Analysis and optimization of CMOS switched-capacitor converters. ISLPED Visvesh S. Sathe, Jae-sun Seo
2015	A	`conf`	Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS. ISLPED Xiaoyang Mi, Debashis Mandal, Visvesh S. Sathe, Bertan Bakkaloglu, Jae-sun Seo
2014	A	`conf`	A deterministic-dither-based, all-digital system for on-chippower supply noise measurement. ISLPED Kannan A. Sankaragomathi, William Anthony Smith, Brian P. Otis, Visvesh S. Sathe
2014	A	`conf`	Quasi-resonant clocking: a run-time control approach for true voltage-frequency-scalability. ISLPED Visvesh S. Sathe
2013	—	`conf`	Energy efficient SoC design. CICC Visvesh S. Sathe, Arif Rahman
2013	J	`jnl`	Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor. IEEE J. Solid State Circuits Visvesh S. Sathe, Srikanth Arekapudi, Alexander T. Ishii, Charles Ouyang, Marios C. Papaefthymiou, Samuel Naffziger
2012	—	`conf`	Advances in 3D design and optimization. CICC Steven J. E. Wilton, Visvesh S. Sathe
2012	J	`jnl`	Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic. IEEE Trans. Very Large Scale Integr. Syst. Jerry C. Kao, Wei-Hsiang Ma, Visvesh S. Sathe, Marios C. Papaefthymiou
2012	—	`conf`	Resonant clock design for a power-efficient high-volume x86-64 microprocessor. ISSCC Visvesh S. Sathe, Srikanth Arekapudi, Charles Ouyang, Marios C. Papaefthymiou, Alexander T. Ishii, Samuel Naffziger
2010	J	`jnl`	187 MHz Subthreshold-Supply Charge-Recovery FIR. IEEE J. Solid State Circuits Wei-Hsiang Ma, Jerry C. Kao, Visvesh S. Sathe, Marios C. Papaefthymiou
2010	—	`conf`	A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm ISSCC Hanh-Phuc Le, Michael D. Seeman, Seth Sanders, Visvesh S. Sathe, Samuel Naffziger, Elad Alon
2009	—	`conf`	A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead. ESSCIRC Jerry C. Kao, Wei-Hsiang Ma, Visvesh S. Sathe, Marios C. Papaefthymiou
2009	—	`conf`	A resonant-clock 200MHz ARM926EJ-STM microcontroller. ESSCIRC Alexander T. Ishii, Jerry C. Kao, Visvesh S. Sathe, Marios C. Papaefthymiou
2008	J	`jnl`	Resonant-Clock Latch-Based Design. IEEE J. Solid State Circuits Visvesh S. Sathe, Jerry C. Kao, Marios C. Papaefthymiou
2007	—	`conf`	A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches. CICC Visvesh S. Sathe, Jerry C. Kao, Marios C. Papaefthymiou
2007	J	`jnl`	Energy-Efficient GHz-Class Charge-Recovery Logic. IEEE J. Solid State Circuits Visvesh S. Sathe, Juang-Ying Chueh, Marios C. Papaefthymiou
2006	—	`conf`	900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading. CICC Juang-Ying Chueh, Visvesh S. Sathe, Marios C. Papaefthymiou
2006	—	`conf`	A 1.1ghz charge-recovery logic. ISSCC Visvesh S. Sathe, Juang-Ying Chueh, Marios Papaefthymio
2005	A	`conf`	A GHz-class charge recovery logic. ISLPED Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler
2005	—	`conf`	Boost Logic: A High Speed Energy Recovery Circuit Family. ISVLSI Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler
2005	—	`conf`	Fast, efficient, recovering, and irreversible. Conf. Computing Frontiers Visvesh S. Sathe, Juang-Ying Chueh, Joohee Kim, Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou
2004	—	`conf`	A synchronous interface for SoCs with multiple clock domains. SoCC Visvesh S. Sathe, Conrad H. Ziesler, Marios C. Papaefthymiou, Suhwan Kim, Stephen V. Kosonocky
2003	A	`conf`	A 225 MHz resonant clocked ASIC chip. ISLPED Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe, Marios C. Papaefthymiou