Vishwani D. Agrawal

486 papers A* 20A 48B 4C 9Misc 84Journal 256Unranked 64

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2025	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2025	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2025	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2025	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2025	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2024	J	`jnl`	A Survey and Recent Advances: Machine Intelligence in Electronic Testing. J. Electron. Test. Soham Roy, Spencer K. Millican, Vishwani D. Agrawal
2024	Misc	`conf`	An Amalgamated Testability Measure Derived from Machine Intelligence. VLSID Soham Roy, Vishwani D. Agrawal
2024	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2024	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2024	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2024	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2024	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2024	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2024	A	`conf`	Unsupervised Learning Provides Intelligence for Testing Hard to Detect Faults. ITC Soham Roy, Vishwani D. Agrawal
2023	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2023	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2023	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2023	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2023	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2022	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2022	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2022	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2022	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2022	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2022	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2022	Misc	`conf`	Fault Modeling and Test Generation for Technology-Specific Defects of Skyrmion Logic Circuits. VTS Ziqi Zhou, Ujjwal Guin, Peng Li, Vishwani D. Agrawal
2021	Misc	`conf`	Defect Characterization and Testing of Skyrmion-Based Logic Circuits. VTS Ziqi Zhou, Ujjwal Guin, Peng Li, Vishwani D. Agrawal
2021	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2021	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2021	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2021	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2021	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2021	J	`jnl`	Estimating Operational Age of an Integrated Circuit. J. Electron. Test. Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal
2021	Misc	`conf`	Special Session - Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits. VTS Soham Roy, Spencer K. Millican, Vishwani D. Agrawal
2021	Misc	`conf`	Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator. VLSID Soham Roy, Spencer K. Millican, Vishwani D. Agrawal
2021	B	`conf`	Unsupervised Learning in Test Generation for Digital Integrated Circuits. ETS Soham Roy, Spencer K. Millican, Vishwani D. Agrawal
2020	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2020	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2020	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2020	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2020	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2020	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2020	J	`jnl`	Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures. J. Electron. Test. Soham Roy, Brandon Stiene, Spencer K. Millican, Vishwani D. Agrawal
2020	A	`conf`	Machine Intelligence for Efficient Test Pattern Generation. ITC Soham Roy, Spencer K. Millican, Vishwani D. Agrawal
2020	Misc	`conf`	Message from the Steering Committee Chair. VLSID Vishwani D. Agrawal
2020	Misc	`conf`	Special Session: Survey of Test Point Insertion for Logic Built-in Self-test. VTS Yang Sun, Spencer K. Millican, Vishwani D. Agrawal
2019	—	`conf`	Applying Neural Networks to Delay Fault Testing: Test Point Insertion and Random Circuit Training. ATS Spencer K. Millican, Yang Sun, Soham Roy, Vishwani D. Agrawal
2019	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2019	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2019	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2019	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2019	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2019	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2019	Misc	`conf`	Energy Efficient Power Distribution on Many-Core SoC. VLSID Mustafa M. Shihab, Vishwani D. Agrawal
2019	—	`conf`	Improved Random Pattern Delay Fault Coverage Using Inversion Test Points. NATW Soham Roy, Brandon Stiene, Spencer K. Millican, Vishwani D. Agrawal
2019	Misc	`conf`	Special Session: Delay Fault Testing - Present and Future. VTS Jubayer Mahmod, Spencer K. Millican, Ujjwal Guin, Vishwani D. Agrawal
2019	—	`conf`	Technology Characterization Model and Scaling for Energy Management. VDAT Harshil Goyal, Vishwani D. Agrawal
2019	Misc	`conf`	Two-Pattern ∆IDDQ Test for Recycled IC Detection. VLSID Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal
2018	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2018	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2018	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2018	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2018	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2018	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2018	Misc	`conf`	Modeling and test generation for combinational hardware Trojans. VTS Ziqi Zhou, Ujjwal Guin, Vishwani D. Agrawal
2017	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2017	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2017	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2017	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2017	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2017	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2017	J	`jnl`	Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling. J. Electron. Test. Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal
2017	J	`jnl`	Three-Stage Optimization of Pre-Bond Diagnosis of TSV Defects. J. Electron. Test. Bei Zhang, Vishwani D. Agrawal
2016	J	`jnl`	Applications of Mixed-Signal Technology in Digital Testing. J. Electron. Test. Baohu Li, Vishwani D. Agrawal
2016	Misc	`conf`	Database Search and ATPG - Interdisciplinary Domains and Algorithms. VLSID Muralidharan Venkatasubramanian, Vishwani D. Agrawal
2016	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2016	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2016	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2016	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2016	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2016	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2016	—	`conf`	Failures Guide Probabilistic Search for a Hard-to-Find Test. NATW Muralidharan Venkatasubramanian, Vishwani D. Agrawal
2015	J	`jnl`	A Maximum Power Algorithm to Find Frequencies for Aperiodic Clock Testing. J. Electron. Test. Sindhu Gunasekar, Vishwani D. Agrawal
2015	—	`conf`	Adopting multi-valued logic for reduced pin-count testing. LATS Baohu Li, Bei Zhang, Vishwani D. Agrawal
2015	—	`conf`	Characterizing Processors for Energy and Performance Management. MTV Harshit Goyal, Vishwani D. Agrawal
2015	J	`jnl`	Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests. J. Electron. Test. Suraj Sindia, Vishwani D. Agrawal
2015	Misc	`conf`	Diagnostic Tests for Pre-bond TSV Defects. VLSID Bei Zhang, Vishwani D. Agrawal
2015	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2015	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2015	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2015	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2015	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2015	Misc	`conf`	Few Good Frequencies for Power-Constrained Test. VLSID Sindhu Gunasekar, Vishwani D. Agrawal
2015	—	`conf`	Message from the LATS2015 Chairs. LATS Víctor H. Champac, Yervant Zorian, Letícia Maria Bolzani Pöhls, Vishwani D. Agrawal
2015	—	`conf`	Multivalued Logic for Reduced Pin Count and Multi-site SoC Testing. NATW Baohu Li, Vishwani D. Agrawal
2015	—	`conf`	Quest for a quantum search algorithm for testing stuck-at faults in digital circuits. DFTS Muralidharan Venkatasubramanian, Vishwani D. Agrawal, James J. Janaher
2015	—	`conf`	Securing IEEE 1687-2014 Standard Instrumentation Access by LFSR Key. ATS Hejia Liu, Vishwani D. Agrawal
2015	—	`conf`	SoC TAM Design to Minimize Test Application Time. NATW Huiting Zhang, Vishwani D. Agrawal
2014	J	`jnl`	A Four-Transistor Level Converter for Dual-Voltage Low-Power Design. J. Low Power Electron. Karthik Naishathrala Jayaraman, Vishwani D. Agrawal
2014	—	`conf`	A New Test Vector Search Algorithm for a Single Stuck-at Fault Using Probabilistic Correlation. NATW Muralidharan Venkatasubramanian, Vishwani D. Agrawal
2014	J	`jnl`	A Novel Wafer Manipulation Method for Yield Improvement and Cost Reduction of 3D Wafer-on-Wafer Stacked ICs. J. Electron. Test. Bei Zhang, Vishwani D. Agrawal
2014	J	`jnl`	A Test Time Theorem and its Applications. J. Electron. Test. Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal
2014	C	`conf`	An optimized diagnostic procedure for pre-bond TSV defects. ICCD Bei Zhang, Vishwani D. Agrawal
2014	J	`jnl`	Diagnostic Test Generation for Transition Delay Faults Using Stuck-At Fault Detection Tools. J. Electron. Test. Yu Zhang, Bei Zhang, Vishwani D. Agrawal
2014	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2014	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2014	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2014	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2014	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2014	—	`conf`	Optimal Selection of ATE Frequencies for Test Time Reduction Using Aperiodic Clock. NATW Sindhu Gunasekar, Vishwani D. Agrawal
2014	—	`conf`	Specification test minimization for given defect level. LATW Suraj Sindia, Vishwani D. Agrawal
2013	—	`conf`	A test time theorem and its applications. LATW Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal
2013	A	`conf`	ATE test time reduction using asynchronous clock period. ITC Praveen Venkataramani, Vishwani D. Agrawal
2013	—	`conf`	Defect Diagnosis of Digital Circuits Using Surrogate Faults. VDAT Chidambaram Alagappan, Vishwani D. Agrawal
2013	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2013	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2013	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2013	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2013	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2013	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2013	J	`jnl`	Eliminating the Timing Penalty of Scan. J. Electron. Test. Ozgur Sinanoglu, Vishwani D. Agrawal
2013	J	`jnl`	Energy-Efficient Dual-Voltage Design Using Topological Constraints. J. Low Power Electron. Mridula Allani, Vishwani D. Agrawal
2013	Misc	`conf`	Finding best voltage and frequency to shorten power-constrained test time. VTS Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal
2013	A	`conf`	High sensitivity test signatures for unconventional analog circuit test paradigms. ITC Suraj Sindia, Vishwani D. Agrawal
2013	J	`jnl`	Neural Network Guided Spatial Fault Resilience in Array Processors. J. Electron. Test. Suraj Sindia, Vishwani D. Agrawal
2013	Misc	`conf`	Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages. VLSI Design Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal
2013	C	`conf`	Power-aware SoC test optimization through dynamic voltage and frequency scaling. VLSI-SoC Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal
2013	Misc	`conf`	Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage. VLSI Design Praveen Venkataramani, Vishwani D. Agrawal
2013	—	`conf`	Yield analysis of a novel wafer manipulation method in 3D stacking. 3DIC Bei Zhang, Baohu Li, Vishwani D. Agrawal
2012	Misc	`ed.`	25th International Conference on VLSI Design, Hyderabad, India, January 7-11, 2012 VLSI Design Vishwani D. Agrawal, Srimat T. Chakradhar
2012	J	`jnl`	Data-Driven DPPM Estimation and Adaptive Fault Coverage Calibration Using MATLAB®. J. Electron. Test. Kanad Chakraborty, Vishwani D. Agrawal
2012	J	`jnl`	Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing. J. Electron. Test. Suraj Sindia, Vishwani D. Agrawal, Virendra Singh
2012	J	`jnl`	Diagnostic Test Set Minimization and Full-Response Fault Dictionary. J. Electron. Test. Mohammed Ashfaq Shukoor, Vishwani D. Agrawal
2012	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2012	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2012	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2012	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2012	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2012	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2012	Misc	`conf`	Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock. VLSI Design Priyadharshini Shanmugasundaram, Vishwani D. Agrawal
2012	C	`conf`	Impact of process variations on computers used for image processing. ISCAS Suraj Sindia, Fa Foster Dai, Vishwani D. Agrawal, Virendra Singh
2012	Misc	`conf`	Keynote Talk: A History of the VLSI Design Conference. VLSI Design Vishwani D. Agrawal
2012	Misc	`conf`	Net diagnosis using stuck-at and transition fault models. VTS Lixing Zhao, Vishwani D. Agrawal
2012	—	`conf`	Optimal power-constrained SoC test schedules with customizable clock rates. SoCC Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal
2012	J	`jnl`	Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients. J. Electron. Test. Suraj Sindia, Vishwani D. Agrawal, Virendra Singh
2012	—	`conf`	Power Problems in VLSI Circuit Testing. VDAT Farhana Rashid, Vishwani D. Agrawal
2012	—	`conf`	Retiming scan circuit to eliminate timing penalty. LATW Ozgur Sinanoglu, Vishwani D. Agrawal
2012	—	`conf`	Tailoring Tests for Functional Binning of Integrated Circuits. Asian Test Symposium Suraj Sindia, Vishwani D. Agrawal
2012	Misc	`conf`	Towards spatial fault resilience in array processors. VTS Suraj Sindia, Vishwani D. Agrawal
2011	Misc	`conf`	An efficient test data reduction technique through dynamic pattern mixing across multiple fault models. VTS Srinivasulu Alampally, R. T. Venkatesh, Priyadharshini Shanmugasundaram, Rubin A. Parekhji, Vishwani D. Agrawal
2011	Misc	`conf`	Dynamic scan clock control for test time reduction maintaining peak power limit. VTS Priyadharshini Shanmugasundaram, Vishwani D. Agrawal
2011	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2011	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2011	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2011	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2011	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2011	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2011	—	`conf`	Minimum energy CMOS design with dual subthreshold supply and multiple logic-level gates. ISQED Kyungseok Kim, Vishwani D. Agrawal
2011	Misc	`conf`	Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients. VTS Suraj Sindia, Vishwani D. Agrawal, Virendra Singh
2011	C	`conf`	Reduced complexity test generation algorithms for transition fault diagnosis. ICCD Yu Zhang, Vishwani D. Agrawal
2011	—	`conf`	Test and Diagnosis of Analog Circuits Using Moment Generating Functions. Asian Test Symposium Suraj Sindia, Vishwani D. Agrawal, Virendra Singh
2011	—	`conf`	Testing for faults, looking for defects. LATW Vishwani D. Agrawal
2011	—	`conf`	Testing linear and non-linear analog circuits using moment generating functions. LATW Suraj Sindia, Vishwani D. Agrawal, Virendra Singh
2011	Misc	`conf`	True Minimum Energy Design Using Dual Below-Threshold Supply Voltages. VLSI Design Kyungseok Kim, Vishwani D. Agrawal
2011	J	`jnl`	Ultra Low Energy CMOS Logic Using Below-Threshold Dual-Voltage Supply. J. Low Power Electron. Kyungseok Kim, Vishwani D. Agrawal
2010	B	`conf`	A diagnostic test generation system and a coverage metric. ETS Yu Zhang, Vishwani D. Agrawal
2010	A	`conf`	A diagnostic test generation system. ITC Yu Zhang, Vishwani D. Agrawal
2010	—	`conf`	An algorithm for diagnostic fault simulation. LATW Yu Zhang, Vishwani D. Agrawal
2010	Misc	`conf`	Application of signal and noise theory to digital VLSI testing. VTS Nitin Yogi, Vishwani D. Agrawal
2010	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2010	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2010	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2010	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2010	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2010	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2010	Misc	`conf`	Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients. VLSI Design Suraj Sindia, Virendra Singh, Vishwani D. Agrawal
2010	—	`conf`	Soft error rate determination for nanoscale sequential logic. ISQED Fan Wang, Vishwani D. Agrawal
2009	B	`conf`	A Two Phase Approach for Minimal Diagnostic Test Set Generation. ETS Mohammed Ashfaq Shukoor, Vishwani D. Agrawal
2009	—	`conf`	Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations. ISVLSI Jins D. Alexander, Vishwani D. Agrawal
2009	C	`conf`	Designing Variation-tolerance in Mixed-signal Components of a System-on-chip. ISCAS Wei Jiang, Vishwani D. Agrawal
2009	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2009	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2009	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2009	—	`conf`	Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients. Asian Test Symposium Suraj Sindia, Virendra Singh, Vishwani D. Agrawal
2009	B	`conf`	On Minimization of Peak Power for Scan Circuit during Test. ETS Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Vishwani D. Agrawal
2009	Misc	`conf`	Output Hazard-Free Transition Delay Fault Test Generation. VTS Sreekumar Menon, Adit D. Singh, Vishwani D. Agrawal
2009	—	`conf`	Polynomial coefficient based DC testing of non-linear analog circuits. ACM Great Lakes Symposium on VLSI Suraj Sindia, Virendra Singh, Vishwani D. Agrawal
2009	Misc	`conf`	Soft Error Rates with Inertial and Logical Masking. VLSI Design Fan Wang, Vishwani D. Agrawal
2009	J	`jnl`	Variable Input Delay CMOS Logic for Low Power Design. IEEE Trans. Very Large Scale Integr. Syst. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
2008	A	`conf`	A tutorial on test power. ISLPED Vishwani D. Agrawal
2008	A	`conf`	Built-in Self-Calibration of On-chip DAC and ADC. ITC Wei Jiang, Vishwani D. Agrawal
2008	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2008	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2008	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2008	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2008	Misc	`conf`	Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. VTS Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal
2008	—	`conf`	Sequential Circuit BIST Synthesis Using Spectrum and Noise from ATPG Patterns. ATS Nitin Yogi, Vishwani D. Agrawal
2008	Misc	`conf`	Single Event Upset: An Embedded Tutorial. VLSI Design Fan Wang, Vishwani D. Agrawal
2008	Misc	`conf`	Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation. VLSI Design Yuanlin Lu, Vishwani D. Agrawal
2007	Misc	`conf`	A Reduced Complexity Algorithm for Minimizing N-Detect Tests. VLSI Design Kalyana R. Kantipudi, Vishwani D. Agrawal
2007	Misc	`conf`	Delay Test Quality Evaluation Using Bounded Gate Delays. VTS Soumitra Bose, Vishwani D. Agrawal
2007	A	`conf`	Delay fault simulation with bounded gate delay mode. ITC Soumitra Bose, Hillary Grimes, Vishwani D. Agrawal
2007	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2007	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2007	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2007	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2007	A	`conf`	Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis. ITC Soumitra Bose, Vishwani D. Agrawal
2007	J	`jnl`	Graphical I IEEE Trans. Very Large Scale Integr. Syst. Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal
2007	A	`conf`	SPARTAN: a spectral and information theoretic approach to partial-scan. ITC Omar I. Khan, Michael L. Bushnell, Suresh Kumar Devanathan, Vishwani D. Agrawal
2007	Misc	`conf`	Spectral RTL Test Generation for Microprocessors. VLSI Design Nitin Yogi, Vishwani D. Agrawal
2007	Misc	`conf`	Statistical Leakage and Timing Optimization for Submicron Process Variation. VLSI Design Yuanlin Lu, Vishwani D. Agrawal
2006	J	`jnl`	CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff. J. Low Power Electron. Yuanlin Lu, Vishwani D. Agrawal
2006	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2006	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2006	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2006	A	`conf`	Fault Coverage Estimation for Non-Random Functional Input Sequences. ITC Soumitra Bose, Vishwani D. Agrawal
2006	A	`conf`	Input-specific dynamic power optimization for VLSI circuits. ISLPED Fei Hu, Vishwani D. Agrawal
2006	—	`conf`	Spectral RTL Test Generation for Gate-Level Stuck-at Faults. ATS Nitin Yogi, Vishwani D. Agrawal
2006	J	`jnl`	Transistor Sizing of Logic Gates to Maximize Input Delay Variability. J. Low Power Electron. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
2006	Misc	`conf`	Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring. VTS Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram
2005	A	`conf`	A random access scans architecture to reduce hardware overhead. ITC Anand S. Mudlapur, Vishwani D. Agrawal, Adit D. Singh
2005	J	`jnl`	Combinational automatic test pattern generation for acyclic sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja
2005	—	`conf`	Concurrent Test Generation. Asian Test Symposium Vishwani D. Agrawal, Alok S. Doshi
2005	—	`conf`	Design of Variable Input Delay Gates for Low Dynamic Power Circuits. PATMOS Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
2005	A	`conf`	Diagnostic and Detection Fault Collapsing for Multiple Output Circuits. DATE Raja K. K. R. Sandireddy, Vishwani D. Agrawal
2005	—	`conf`	Dual-transition glitch filtering in probabilistic waveform power estimation. ACM Great Lakes Symposium on VLSI Fei Hu, Vishwani D. Agrawal
2005	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2005	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2005	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2005	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2005	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2005	C	`conf`	Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis. ICCD Fei Hu, Vishwani D. Agrawal
2005	—	`conf`	Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for V PATMOS Yuanlin Lu, Vishwani D. Agrawal
2005	Misc	`conf`	Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies. VLSI Design Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell
2005	Misc	`conf`	Variable Input Delay CMOS Logic for Low Power Design. VLSI Design Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
2004	J	`jnl`	1985 to 1987: My years with D&T. IEEE Des. Test Comput. Vishwani D. Agrawal
2004	J	`jnl`	A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults. J. Comput. Sci. Technol. Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell
2004	Misc	`conf`	A Tuturial on the Emerging Nanotechnology Devices. VLSI Design Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
2004	Misc	`conf`	CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. VLSI Design Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
2004	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2004	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2004	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2004	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2004	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2004	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2004	A	`conf`	On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits. ITC Junwu Zhang, Michael L. Bushnell, Vishwani D. Agrawal
2003	Misc	`conf`	A Fault-Independent Transitive Closure Algorithm for Redundancy Identification. VLSI Design Vishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell
2003	J	`jnl`	A test evaluation technique for VLSI circuits using register-transfer level fault modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul
2003	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2003	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2003	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2003	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2003	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2003	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2003	Misc	`conf`	Exclusive Test and its Applications to Fault Diagnosis. VLSI Design Vishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja
2003	A	`conf`	Fault Collapsing via Functional Dominance. ITC Vishwani D. Agrawal, A. V. S. S. Prasad, Madhusudan V. Atre
2003	Misc	`conf`	Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. VLSI Design Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
2003	Misc	`conf`	New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. VLSI Design Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal
2002	A	`conf`	A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets. ITC A. V. S. S. Prasad, Vishwani D. Agrawal, Madhusudan V. Atre
2002	—	`conf`	A New Transitive Closure Algorithm with Application to Redundancy Identification. DELTA Vivek Gaur, Vishwani D. Agrawal, Michael L. Bushnell
2002	A	`conf`	Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects. ITC Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal
2002	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2002	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2002	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2002	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2002	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2002	—	`conf`	Electronic Testing for SOC Designers (Tutorial Abstract). ASP-DAC/VLSI Design Vishwani D. Agrawal, Michael L. Bushnell
2002	—	`conf`	Multiple Faults: Modeling, Simulation and Test. ASP-DAC/VLSI Design Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja
2002	J	`jnl`	State and Fault Information for Compaction-Based Test Generation. J. Electron. Test. Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal
2001	Misc	`conf`	Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model. VLSI Design Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal
2001	A	`conf`	Combinational test generation for various classes of acyclic sequential circuits. ITC Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja
2001	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2001	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2001	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2001	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2001	A	`conf`	Efficient spectral techniques for sequential ATPG. DATE Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal
2001	Misc	`conf`	Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment. VTS Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal
2000	—	`conf`	A testability metric for path delay faults and its application. ASP-DAC Huan-Chih Tsai, Kwang-Ting Cheng, Vishwani D. Agrawal
2000	Misc	`conf`	Choice of Tests for Logic Verification and Equivalence Checking. VLSI Design Vishwani D. Agrawal
2000	—	`conf`	Collaboration between Industry and Academia in Test Research. Asian Test Symposium Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu
2000	—	`conf`	Compaction-based test generation using state and fault information. Asian Test Symposium Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal
2000	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2000	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2000	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2000	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2000	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
2000	J	`jnl`	False-Path Removal Using Delay Fault Simulation. J. Electron. Test. Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi
2000	J	`jnl`	Improving path delay testability of sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
2000	J	`jnl`	Path delay fault simulation of sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
2000	A	`conf`	Reducing the Complexity of Defect Level Modeling Using the Clustering Effect. DATE José T. de Sousa, Vishwani D. Agrawal
2000	A	`conf`	Register-transfer level fault modeling and test evaluation techniques for VLSI circuits. ITC Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul
2000	—	`conf`	Testing in the Fourth Dimension. Asian Test Symposium Vishwani D. Agrawal, Kwang-Ting Cheng
1999	Misc	`conf`	A Complete Characterization of Path Delay Faults through Stuck-at Faults. VLSI Design Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell
1999	—	`conf`	A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability. Great Lakes Symposium on VLSI Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal
1999	Misc	`conf`	A Test Generator for Segment Delay Faults. VLSI Design Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
1999	Misc	`conf`	Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. VLSI Design Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss
1999	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1999	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1999	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1999	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1999	A	`conf`	Panel: Increasing test coverage in a VLSI desgin course. ITC Vishwani D. Agrawal
1999	Misc	`conf`	Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test. VTS Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul
1998	A	`conf`	A non-enumerative path delay fault simulator for sequential circuits. ITC Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu
1998	J	`jnl`	A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
1998	J	`jnl`	A rated-clock test method for path delay faults. IEEE Trans. Very Large Scale Integr. Syst. Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
1998	J	`jnl`	Deriving Logic Systems for Path Delay Test Generation. IEEE Trans. Computers Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
1998	J	`jnl`	Design of mixed-signal systems for testability. Integr. Vishwani D. Agrawal
1998	J	`jnl`	Editorial. Des. Autom. Embed. Syst. Vishwani D. Agrawal
1998	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1998	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1998	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1998	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1998	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1998	—	`conf`	False-Path Removal Using Delay Fault Simulation. Asian Test Symposium Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell
1998	Misc	`conf`	Mixed-Signal Test. VLSI Design Ananta K. Majhi, Vishwani D. Agrawal
1998	—	`conf`	Mutually Disjoint Signals and Probability Calculation in Digital Circuits. Great Lakes Symposium on VLSI Vishwani D. Agrawal, Sharad C. Seth
1998	J	`jnl`	Numerical computation of characteristic polynomials of Boolean functions and its applications. Numer. Algorithms Vishwani D. Agrawal, David Lee, Henryk Wozniakowski
1998	Misc	`conf`	On Delay-Untestable Paths and Stuck-Fault Redundancy. VTS Subhashis Majumder, Vishwani D. Agrawal, Michael L. Bushnell
1998	Misc	`conf`	Optimizing Logic Design Using Boolean Transforms. VLSI Design Pramit Chavda, James Jacob, Vishwani D. Agrawal
1998	Misc	`conf`	Path Delay Testing: Variable-Clock Versus Rated-Clock. VLSI Design Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal
1998	J	`jnl`	Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits. J. Electron. Test. Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas
1998	J	`jnl`	The path-status graph with application to delay fault simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
1998	Misc	`conf`	Tutorial: Delay Fault Models and Coverage. VLSI Design Ananta K. Majhi, Vishwani D. Agrawal
1997	Misc	`conf`	Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs. VLSI Design James Jacob, P. Srinivas Sivakumar, Vishwani D. Agrawal
1997	A	`conf`	Algorithms for Switch Level Delay Fault Simulation. ITC Soumitra Bose, Vishwani D. Agrawal, Thomas G. Szymanski
1997	J	`jnl`	Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests. J. Electron. Test. Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
1997	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1997	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1997	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1997	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1997	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1997	A	`conf`	Effective Path Selection for Delay Fault Testing of Sequential Circuits. ITC Tapan J. Chakraborty, Vishwani D. Agrawal
1997	A	`conf`	Fast identification of untestable delay faults using implications. ICCAD Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
1997	Misc	`conf`	Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation. VLSI Design Mandyam-Komar Srinivas, Michael L. Bushnell, Vishwani D. Agrawal
1997	J	`jnl`	Improving a nonenumerative method to estimate path delay fault coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel
1997	Misc	`conf`	Low-Power Design by Hazard Filtering. VLSI Design Vishwani D. Agrawal
1997	J	`jnl`	On variable clock methods for path delay testing of sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
1997	Misc	`conf`	Power Dissipation During Testing: Should We Worry About it? VTS Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian
1997	J	`jnl`	Redundancy removal and test generation for circuits with non-Boolean primitives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srimat T. Chakradhar, Steven G. Rothweiler, Vishwani D. Agrawal
1997	J	`jnl`	Scheduling tests for VLSI systems under power constraints. IEEE Trans. Very Large Scale Integr. Syst. Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal
1996	J	`jnl`	1995 Asian Test Symposium carves a niche. IEEE Des. Test Comput. Vishwani D. Agrawal
1996	A	`conf`	An Exact Non-Enumerative Fault Simulator for Path-Delay Faults. ITC Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
1996	Misc	`conf`	Characteristic polynomial method for verification and test of combinational circuits. VLSI Design Vishwani D. Agrawal, David Lee
1996	Misc	`conf`	Design for high-speed testability of stuck-at faults. VLSI Design Tapan J. Chakraborty, Vishwani D. Agrawal
1996	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1996	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1996	J	`jnl`	Functional test generation for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal
1996	—	`conf`	Improving Circuit Testability by Clock Control. Great Lakes Symposium on VLSI Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal
1996	Misc	`conf`	Improving accuracy in path delay fault coverage estimation. VLSI Design Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
1996	Misc	`conf`	On test coverage of path delay faults. VLSI Design Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal
1996	Misc	`conf`	Parallel concurrent path-delay fault simulation using single-input change patterns. VLSI Design Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
1996	—	`conf`	Redundancy Identification Using Transitive Closure. Asian Test Symposium Vishwani D. Agrawal, Michael L. Bushnell, Qing Lin
1996	A	`conf`	SIGMA: a simulator for segment delay faults. ICCAD Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
1996	Misc	`conf`	Science, Technology, and the Indian Society. VLSI Design Vishwani D. Agrawal
1996	Misc	`conf`	Segment delay faults: a new fault model. VTS Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
1996	Misc	`conf`	Statistical path delay fault coverage estimation for synchronous sequential circuits. VLSI Design Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas
1996	A	`conf`	Synthesis of Self-Testing Finite State Machines from High-Level Specifications. ITC Vishwani D. Agrawal, Ronald D. Blanton, Maurizio Damiani
1995	J	`jnl`	A partition and resynthesis approach to testable design of large circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal
1995	—	`conf`	An adaptive distributed algorithm for sequential circuit test generation. EURO-DAC James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal
1995	Misc	`conf`	An asynchronous algorithm for sequential circuit test generation on a network of workstations. VLSI Design James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal
1995	Misc	`conf`	An efficient automatic test generation system for path delay faults in combinational circuits. VLSI Design Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal
1995	J	`jnl`	An exact algorithm for selecting partial scan flip-flops. J. Electron. Test. Srimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal
1995	A	`conf`	Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests. ITC Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
1995	J	`jnl`	Combinational ATPG theorems for identifying untestable faults in sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vishwani D. Agrawal, Srimat T. Chakradhar
1995	J	`jnl`	Editorial - Special issue on partial scan design. J. Electron. Test. Vishwani D. Agrawal
1995	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1995	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1995	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1995	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1995	J	`jnl`	Energy models for delay testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srimat T. Chakradhar, Mahesh A. Iyer, Vishwani D. Agrawal
1995	J	`jnl`	Fault coverage estimation by test vector sampling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
1995	Misc	`conf`	Functional test generation for non-scan sequential circuits. VLSI Design Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal
1995	—	`conf`	Functional test generation for path delay faults. Asian Test Symposium Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell
1995	A	`conf`	High-Performance Circuit Testing with Slow-Speed Testers. ITC Vishwani D. Agrawal, Tapan J. Chakraborty
1995	—	`conf`	Panel: New Research Problems in the Emerging Test Technology. Asian Test Symposium Vishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, Sandip Kundu, Chung-Len Lee, Yinghua Min, Parimal Pal Chaudhuri
1995	Misc	`conf`	Robust testing for stuck-at faults. VLSI Design Tapan J. Chakraborty, Vishwani D. Agrawal
1995	—	`conf`	Sequential logic path delay test generation by symbolic analysis. Asian Test Symposium Soumitra Bose, Vishwani D. Agrawal
1995	Misc	`conf`	Simulation of at-speed tests for stuck-at faults. VTS Tapan J. Chakraborty, Vishwani D. Agrawal
1995	Misc	`conf`	Statistical methods for delay fault coverage analysis. VLSI Design Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
1995	J	`jnl`	Test Generation for Path Delay Faults Using Binary Decision Diagrams. IEEE Trans. Computers Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal
1995	J	`jnl`	Test function embedding algorithms with application to interconnected finite state machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal
1994	Misc	`conf`	A Test Function Architecture for Interconnected Finite State Machines. VLSI Design Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal
1994	J	`jnl`	A tale of two designs: the cheapest and the most economic. J. Electron. Test. Vishwani D. Agrawal
1994	A*	`conf`	An Efficient Path Delay Fault Coverage Estimator. DAC Keerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal
1994	A*	`conf`	An Exact Algorithm for Selecting Partial Scan Flip-Flops. DAC Srimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal
1994	Misc	`conf`	An Improved Deductive Fault Simulator. VLSI Design P. R. Suresh Kumar, James Jacob, Mandyam-Komar Srinivas, Vishwani D. Agrawal
1994	—	`book`	Concurrent and comparative discrete event simulation. Ernst G. Ulrich, Vishwani D. Agrawal, Jack H. Arabian
1994	—	`conf`	Delay independent initialization of sequential circuits. Great Lakes Symposium on VLSI Tapan J. Chakraborty, Vishwani D. Agrawal
1994	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1994	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1994	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1994	J	`jnl`	Energy minimization and design for testability. J. Electron. Test. Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell
1994	Misc	`conf`	FACTS: fault coverage estimation by test vector sampling. VTS Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
1994	Misc	`conf`	Power Constraint Scheduling of Tests. VLSI Design Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal
1993	Misc	`conf`	A Path Delay Fault Simulator for Sequential Circuits. VLSI Design Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
1993	A	`conf`	A Synthesis Approach to Design for Testability. ITC Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal
1993	J	`jnl`	A Tutorial on Built-In Self-Test, Part 2: Applications. IEEE Des. Test Comput. Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja
1993	J	`jnl`	A Tutorial on Built-in Self-Test. I. Principles. IEEE Des. Test Comput. Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja
1993	J	`jnl`	A transitive closure algorithm for test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srimat T. Chakradhar, Vishwani D. Agrawal, Steven G. Rothweiler
1993	J	`jnl`	Accurate computation of field reject ratio based on fault latency. IEEE Trans. Very Large Scale Integr. Syst. D. Das, Sharad C. Seth, Vishwani D. Agrawal
1993	—	`conf`	Clock partitioning for testability. Great Lakes Symposium on VLSI Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal
1993	—	`conf`	Delay fault testability evaluation through timing simulation. Great Lakes Symposium on VLSI Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
1993	A*	`conf`	Design for Testability for Path Delay faults in Sequential Circuits. DAC Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
1993	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1993	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1993	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1993	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1993	J	`jnl`	Finite state machine synthesis with fault tolerant test function. J. Electron. Test. Srimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal
1993	J	`jnl`	Generating Tests for Delay Faults in Nonscan Circuits. IEEE Des. Test Comput. Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth
1993	A	`conf`	Generation of Compact Delay Tests by Multiple-Path Activation. ITC Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
1993	—	`conf`	Logic systems for path delay test generation. EURO-DAC Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
1993	Misc	`conf`	Partial scan testing with single clock control. VTS Vishwani D. Agrawal, Tapan J. Chakraborty
1993	J	`jnl`	Path delay fault simulation of sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
1993	A*	`conf`	Sequential Circuit Test Generation on a Distributed System. DAC Prathima Agrawal, Vishwani D. Agrawal, Joan Villoldo
1993	A	`conf`	Test Pattern Generation for Sequential Circuits on a Network of Workstations. HPDC Prathima Agrawal, Vishwani D. Agrawal, Joan Villoldo
1993	—	`conf`	Test function embedding algorithms with application to interconnected finite state machines. EURO-DAC Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal
1993	J	`jnl`	The optimistic update theorem for path delay testing in sequential circuits. J. Electron. Test. Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
1992	Misc	`conf`	A New Method for Generating Tests for Delay Faults in Non-Scan Circuits. VLSI Design Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth
1992	A*	`conf`	Delay Fault Models and Test Generation for Random Logic Sequential Circuits. DAC Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
1992	A*	`conf`	Delay Fault Test Generation for Scan/Hold Circuits Using Boolean Expressions. DAC Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal
1992	—	`conf`	DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits. EURO-DAC Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth
1992	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1992	A*	`conf`	Finite State Machine Synthesis with Fault Tolerant Test Function. DAC Srimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal
1992	—	`conf`	Finite State Machine Testing Based on Growth and Dissappearance Faults. FTCS Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal
1992	Misc	`conf`	Functional Test Generation for Sequential Circuits. VLSI Design James Jacob, Vishwani D. Agrawal
1992	J	`jnl`	Initializability Consideration in Sequential Machine Synthesis. IEEE Trans. Computers Kwang-Ting Cheng, Vishwani D. Agrawal
1992	J	`jnl`	Multiple fault detection in two-level multi-output circuits. J. Electron. Test. James Jacob, Vishwani D. Agrawal
1992	J	`jnl`	Performance Analysis of Synchronized Iterative Algorithms on Multiprocessor Systems. IEEE Trans. Parallel Distributed Syst. Vishwani D. Agrawal, Srimat T. Chakradhar
1992	J	`jnl`	The Comparative and Concurrent Simulation of discrete-event experiments. J. Electron. Test. Ernst G. Ulrich, Karen Lentz, Jack H. Arabian, Michael Gustin, Vishwani D. Agrawal, Pier Luca Montessoro
1991	A*	`conf`	A Transitive Closure Based Algorithm for Test Generation. DAC Srimat T. Chakradhar, Vishwani D. Agrawal
1991	C	`conf`	Design and Test-The Two Sides of a Coin. ICCD Vishwani D. Agrawal
1991	A	`conf`	Estimating the Quality of Manufactured Digital Sequential Circuits. ITC Dharam Vir Das, Sharad C. Seth, Vishwani D. Agrawal
1991	C	`conf`	Stafan Algorithms for MOS Circuits. ICCD Joan Villoldo, Prathima Agrawal, Vishwani D. Agrawal
1990	J	`jnl`	A Partial Scan Method for Sequential Circuits with Feedback. IEEE Trans. Computers Kwang-Ting Cheng, Vishwani D. Agrawal
1990	J	`jnl`	A Simulation-Based Method for Generating Tests for Sequential Circuits. IEEE Trans. Computers Kwang-Ting Cheng, Vishwani D. Agrawal, Ernest S. Kuh
1990	J	`jnl`	A Statistical Theory of Digital Circuit Testability. IEEE Trans. Computers Sharad C. Seth, Vishwani D. Agrawal, Hassan Farhat
1990	A*	`conf`	An Entropy Measure for the Complexity of Multi-Output Boolean Functions. DAC Kwang-Ting Cheng, Vishwani D. Agrawal
1990	—	`conf`	An architecture for synthesis of testable finite state machines. EURO-DAC Vishwani D. Agrawal, Kwang-Ting Cheng
1990	A	`conf`	An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisited. ITC Dharam Vir Das, Sharad C. Seth, Paul T. Wagner, John C. Anderson, Vishwani D. Agrawal
1990	A*	`conf`	Automatic Test Generation Using Quadratic 0-1 Programming. DAC Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell
1990	J	`jnl`	Editorial. J. Electron. Test. Vishwani D. Agrawal
1990	J	`jnl`	Fault Sampling Revisited. IEEE Des. Test Comput. Vishwani D. Agrawal, Hatsuyoshi Kato
1990	J	`jnl`	Finite state machine synthesis with embedded test function. J. Electron. Test. Vishwani D. Agrawal, Kwang-Ting Cheng
1990	A	`conf`	Logic Simulation and Parallel Processing. ICCAD Vishwani D. Agrawal, Srimat T. Chakradhar
1990	J	`jnl`	Neural Net and Boolean Satisfiability Models of Logic Circuits. IEEE Des. Test Comput. Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell, Thomas K. Truong
1990	A	`conf`	Performance estimation in a massively parallel system. SC Vishwani D. Agrawal, Srimat T. Chakradhar
1990	—	`conf`	Polynomial time solvable fault detection problems. FTCS Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell
1990	A*	`conf`	Test Function Specification in Synthesis. DAC Vishwani D. Agrawal, Kwang-Ting Cheng
1990	J	`jnl`	Toward massively parallel automatic test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal
1989	J	`jnl`	A directed search method for test generation using a concurrent simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vishwani D. Agrawal, Kwang-Ting Cheng, Prathima Agrawal
1989	J	`jnl`	A new model for computation of probabilistic testability in combinational circuits. Integr. Sharad C. Seth, Vishwani D. Agrawal
1989	J	`jnl`	A new model for computation of probabilistic testability in combinational circuits. Integr. Sharad C. Seth, Vishwani D. Agrawal
1989	—	`conf`	An economical scan design for sequential logic test generation. FTCS Kwang-Ting Cheng, Vishwani D. Agrawal
1989	A	`conf`	Design of sequential machines for efficient test generation. ICCAD Kwang-Ting Cheng, Vishwani D. Agrawal
1989	A	`conf`	Fault Simulation in a Pipelined Multiprocessor System. ITC Prathima Agrawal, Vishwani D. Agrawal, Kwang-Ting Cheng, Raffi Tutundjian
1989	A	`conf`	State assignment for initializable synthesis (gate level analysis). ICCAD Kwang-Ting Cheng, Vishwani D. Agrawal
1988	—	`conf`	A sequential circuit test generation using threshold-value simulation. FTCS Kwang-Ting Cheng, Vishwani D. Agrawal, Ernest S. Kuh
1988	A	`conf`	Automatic test generation using neural networks. ICCAD Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal
1988	A*	`conf`	Contest: A Concurrent Test Generator for Sequential Circuits. DAC Vishwani D. Agrawal, Kwang-Ting Cheng, Prathima Agrawal
1988	J	`jnl`	Designing circuits with partial scan. IEEE Des. Test Vishwani D. Agrawal, Kwang-Ting Cheng, Daniel D. Johnson, Tonysheng Lin
1988	C	`conf`	Test generation by fault sampling. ICCD Vishwani D. Agrawal, Hassan Farhat, Sharad Seth
1986	A	`conf`	Deterministic Versus Random Testing. ITC Vishwani D. Agrawal, M. Ray Mercer
1985	J	`jnl`	Modeling and Test Generation Algorithms for MOS Circuits. IEEE Trans. Computers Sunil K. Jain, Vishwani D. Agrawal
1985	A*	`conf`	Multiple output minimization. DAC Prathima Agrawal, Vishwani D. Agrawal, Nripendra N. Biswas
1985	A	`conf`	STAFAN Takes a Middle Course. ITC Vishwani D. Agrawal
1985	J	`jnl`	Statistical Fault Analysis. IEEE Des. Test Sunil K. Jain, Vishwani D. Agrawal
1985	—	`conf`	VLSI design process. ACM Conference on Computer Science Vishwani D. Agrawal, Samuel H. C. Poon
1984	A*	`conf`	A gate level model for CMOS combinational logic circuits with application to fault detection. DAC Sudhakar M. Reddy, Vishwani D. Agrawal, Sunil K. Jain
1984	J	`jnl`	Characterizing the LSI Yield Equation from Wafer Test Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sharad C. Seth, Vishwani D. Agrawal
1984	A*	`conf`	Chip layout optimization using critical path weighting. DAC Alfred E. Dunlop, Vishwani D. Agrawal, David N. Deutsch, M. F. Jukl, Patrick Kozak, Manfred Wiesel
1984	A*	`conf`	STAFAN: An alternative to fault simulation. DAC Sunil K. Jain, Vishwani D. Agrawal
1984	A	`conf`	Will Testability Analysis Replace Fault Simulation ? ITC Vishwani D. Agrawal
1983	A*	`conf`	Test generation for MOS circuits using D-algorithm. DAC Sunil K. Jain, Vishwani D. Agrawal
1982	A*	`conf`	Synchronous path analysis in MOS circuit simulator. DAC Vishwani D. Agrawal
1982	A	`conf`	Testability Measures : What Do They Tell Us ? ITC Vishwani D. Agrawal, M. Ray Mercer
1981	J	`jnl`	An Information Theoretic Approach to Digital Fault Testing. IEEE Trans. Computers Vishwani D. Agrawal
1981	A*	`conf`	LSI product quality and fault coverage. DAC Vishwani D. Agrawal, Sharad C. Seth, Prathima Agrawal
1981	A	`conf`	Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation. ITC M. Ray Mercer, Vishwani D. Agrawal, Carlos M. Roman
1980	A*	`conf`	A mixed-mode simulator. DAC Vishwani D. Agrawal, Ajoy K. Bose, Patrick Kozak, Hao N. Nham, Ernesto Pacas-Skewes
1979	J	`jnl`	Author's Reply. IEEE Trans. Computers Vishwani D. Agrawal
1979	J	`jnl`	Comments on "An Approach to Highly Integrated Computer-Maintained Cellular Arrays". IEEE Trans. Computers Vishwani D. Agrawal
1978	J	`jnl`	When to Use Random Testing. IEEE Trans. Computers Vishwani D. Agrawal
1976	J	`jnl`	On Monte Carlo Testing of Logic Tree Networks. IEEE Trans. Computers Prathima Agrawal, Vishwani D. Agrawal
1975	J	`jnl`	Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks. IEEE Trans. Computers Prathima Agrawal, Vishwani D. Agrawal
1972	J	`jnl`	An Automatic Test Generation System for Illiac IV Logic Boards. IEEE Trans. Computers Vishwani D. Agrawal, Prathima Agrawal