Vishnu P. Nambiar

32 papers C 15Journal 10Unranked 7

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	Qubit-State Discrimination using Neural Networks with Rapid and Energy-Efficient Compute Arrays. ISCAS Yuntian Liu, Yi Sheng Chong, Benjamin Lienhard, Minghao Fan, Wang Ling Goh, Vishnu P. Nambiar, Anh Tuan Do
2024	C	`conf`	3881 Gbps/W, 3005 µm AES Core with State Based Clock Gating for IoT applications. ISCAS Zhangyi Pei, Vishnu P. Nambiar, Yi Sheng Chong, Wang Ling Goh, Anh Tuan Do
2024	—	`conf`	A 360 GOPS/W CGRA in a RISC-V SoC with Multi-Hop Routers and Idle-State Instructions for Edge Computing Applications. ISOCC Vishnu P. Nambiar, Y. S. Chong, Thilini Kaushalya Bandara, Dhananjaya Wijerathne, Z. Li, Rohan Juneja, Li-Shiuan Peh, Tulika Mitra, A. T. Do
2024	C	`conf`	A 420 GOPS/W CGRA with a Configurable MAC and Dynamic Truncation. ISCAS Yi Sheng Chong, Rakshith Harish, Rajesh Chandrasekhara Panicker, Vishnu P. Nambiar, Anh Tuan Do
2024	C	`conf`	Exploring Error Correction Circuits on RISC-V based Systems for Space Applications. ISCAS Nazim Altar Koca, Chip-Hong Chang, Anh Tuan Do, Vishnu P. Nambiar
2024	—	`conf`	PACE: A Scalable and Energy Efficient CGRA in a RISC-V SoC for Edge Computing Applications. HCS Vishnu P. Nambiar, Yi Sheng Chong, Thilini Kaushalya Bandara, Dhananjaya Wijerathne, Zhaoying Li, Rohan Juneja, Li-Shiuan Peh, Tulika Mitra, Anh Tuan Do
2024	C	`conf`	Quantum Readout Processing Accelerator with a CORDIC Core at Cryogenic Temperature. ISCAS Yi Sheng Chong, Hongyu Cao, Wang Ling Goh, Patrick Bore, Yuanzheng Paul Tan, Yung Szen Yap, Rainer Dumke, Vishnu P. Nambiar, Anh Tuan Do
2022	C	`conf`	0.08mm ISCAS Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do
2022	C	`conf`	A 1800μm ISCAS Jingjing Lan, Vishnu P. Nambiar, Ming Ming Wong, Fei Li, Yuan Gao, Kevin Tshun Chuan Chai, Anh Tuan Do
2022	J	`jnl`	A 2.5 μW KWS Engine With Pruned LSTM and Embedded MFCC for IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs Yi Sheng Chong, Wang Ling Goh, Vishnu P. Nambiar, Anh-Tuan Do
2022	C	`conf`	Recovering Accuracy of RRAM-based CIM for Binarized Neural Network via Chip-in-the-loop Training. ISCAS Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do
2021	—	`conf`	A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP. ESSCIRC Ming Ming Wong, S. B. Shrestha, Vishnu P. Nambiar, Aarthy Mani, Yun Kwan Lee, Eng-Kiat Koh, W. Jiang, Kevin Tshun Chuan Chai, Anh-Tuan Do
2021	—	`conf`	A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP. ESSDERC Ming Ming Wong, S. B. Shrestha, Vishnu P. Nambiar, Aarthy Mani, Yun Kwan Lee, Eng-Kiat Koh, W. Jiang, Kevin Tshun Chuan Chai, Anh-Tuan Do
2021	J	`jnl`	A 5.28-mm² 4.5-pJ/SOP Energy-Efficient Spiking Neural Network Hardware With Reconfigurable High Processing Speed Neuron Core and Congestion-Aware Router. IEEE Trans. Circuits Syst. I Regul. Pap. Junran Pu, Wang Ling Goh, Vishnu P. Nambiar, Ming Ming Wong, Anh Tuan Do
2021	J	`jnl`	A Low Power and Low Area Router With Congestion-Aware Routing Algorithm for Spiking Neural Network Hardware Implementations. IEEE Trans. Circuits Syst. II Express Briefs Junran Pu, Wang Ling Goh, Vishnu P. Nambiar, Anh-Tuan Do
2021	J	`jnl`	A Low-Cost High-Throughput Digital Design of Biorealistic Spiking Neuron. IEEE Trans. Circuits Syst. II Express Briefs Junran Pu, Wang Ling Goh, Vishnu P. Nambiar, Yi Sheng Chong, Anh Tuan Do
2021	C	`conf`	An Energy-Efficient Convolution Unit for Depthwise Separable Convolutional Neural Networks. ISCAS Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do
2021	C	`conf`	Efficient Implementation of Activation Functions for LSTM accelerators. VLSI-SoC Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do
2021	J	`jnl`	Energy Efficient 0.5V 4.8pJ/SOP 0.93μW Leakage/Core Neuromorphic Processor Design. IEEE Trans. Circuits Syst. II Express Briefs Vishnu P. Nambiar, Junran Pu, Yun Kwan Lee, Aarthy Mani, Eng-Kiat Koh, Ming Ming Wong, Fei Li, Wang Ling Goh, Anh Tuan Do
2020	—	`conf`	0.5V 4.8 pJ/SOP 0.93µW Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron. A-SSCC Vishnu P. Nambiar, Junran Pu, Yun Kwan Lee, Aarthy Mani, Tao Luo, L. Yang, Eng-Kiat Koh, Ming Ming Wong, Fei Li, Wang Ling Goh, Anh Tuan Do
2020	C	`conf`	Post-Silicon Validation Methodology for Resource-Constrained Neuromorphic Hardware. IECON Yun Kwan Lee, Vishnu P. Nambiar, Kim Seng Goh, Anh Tuan Do
2020	C	`conf`	Scalable Block-Based Spiking Neural Network Hardware with a Multiplierless Neuron Model. ISCAS Vishnu P. Nambiar, Eng-Kiat Koh, Junran Pu, Aarthy Mani, Ming Ming Wong, Li Fei, Wang Ling Goh, Anh Tuan Do
2019	C	`conf`	Block-Based Spiking Neural Network Hardware with Deme Genetic Algorithm. ISCAS Junran Pu, Vishnu P. Nambiar, Anh-Tuan Do, Wang Ling Goh
2019	—	`conf`	Coverage Driven Verification Methodology for Asynchronous Neuromorphic Routers. SoCC Yun Kwan Lee, Vishnu P. Nambiar, Junran Pu, Wang Ling Goh, Anh-Tuan Do
2019	—	`conf`	Ower and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing. SoCC Junran Pu, Vishnu P. Nambiar, Aarthy Mani, Wang Ling Goh, Anh-Tuan Do
2017	J	`jnl`	A real-time near infrared image acquisition system based on image quality assessment. J. Real Time Image Process. Yee Hui Lee, Mohamed Khalil Hani, Rabia Bakhteri, Vishnu P. Nambiar
2014	J	`jnl`	Hardware implementation of evolvable block-based neural networks utilizing a cost efficient sigmoid-like activation function. Neurocomputing Vishnu P. Nambiar, Mohamed Khalil Hani, Riadh Sahnoun, Muhammad N. Marsono
2014	J	`jnl`	Optimization of structure and system latency in evolvable block-based neural networks using genetic algorithm. Neurocomputing Vishnu P. Nambiar, Mohamed Khalil Hani, Muhammad N. Marsono, Chen Wei Sia
2013	C	`conf`	Co-simulation methodology for improved design and verification of hardware neural networks. IECON Mohamed Khalil Hani, Vishnu P. Nambiar, Muhammad N. Marsono
2013	J	`jnl`	HW/SW co-design of reconfigurable hardware-based genetic algorithm in FPGAs applicable to a variety of problems. Computing Vishnu P. Nambiar, Sathivellu Balakrishnan, Mohamed Khalil Hani, Muhammad N. Marsono
2012	C	`conf`	GA-based parameter tuning in finger-vein biometric embedded systems for information security. ICCC Mohamed Khalil Hani, Vishnu P. Nambiar, Muhammad N. Marsono
2009	J	`jnl`	Accelerating the AES encryption function in OpenSSL for embedded systems. Int. J. Inf. Commun. Technol. Vishnu P. Nambiar, Mohamed Khalil Hani, Muhammad Munim Ahmad Zabidi