Vishal Saxena - RankMe

58 papers B 2C 9Journal 21Unranked 26

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	Electronic Photonic Integrated Circuits (EPICs): Fundamentals and Applications. ISCAS Vishal Saxena
2024	—	`conf`	A 7×4 Silicon Photonic Reconfigurable Optical Analog Processor with Algorithmic Calibration. OFC Md Jubayer Shawon, Vishal Saxena
2024	C	`conf`	A Sub-1pJ/bit Laser Power Independent 32Gb/s Silicon Photonic EAM Driver in 65nm CMOS. ISCAS Shubham Mishra, Vishal Saxena
2024	—	`conf`	Compact Convolutional SNN Architecture for the Neuromorphic Speech Denoising. MWSCAS Anuar Dorzhigulov, Vishal Saxena
2024	J	`jnl`	Optical Interconnects Using Hybrid Integration of CMOS and Silicon-Photonic ICs. IEEE Trans. Circuits Syst. II Express Briefs Vishal Saxena, Ankur Kumar, Shubham Mishra, Samuel Palermo, Kadaba R. Lakshmikumar
2023	—	`conf`	A Silicon Photonic Reconfigurable Optical Analog Processor (SiROAP) with a 4x4 Optical Mesh. ISSCC Md Jubayer Shawon, Vishal Saxena
2023	—	`conf`	Automatic In-situ Optical Linearization of Silicon Photonic Ring-Assisted MZ Modulator for Integrated RF Photonic SoCs. OFC Md Jubayer Shawon, Vishal Saxena
2023	J	`jnl`	Compact Modeling and Rapid Simulation of Silicon Photonic Micro-Disk and Ring Modulators. CoRR Vishal Saxena, Md Jubayer Shawon
2023	C	`conf`	Power Linear DACs (PLDACs) for Configuration and Control of Silicon Photonic Integrated Circuits. ISCAS Vikas Kumar, Shubham Mishra, Vishal Saxena
2022	J	`jnl`	A Deep Unsupervised Feature Learning Spiking Neural Network With Binarized Classification Layers for the EMNIST Classification. IEEE Trans. Emerg. Top. Comput. Intell. Ruthvik Vaila, John N. Chiasson, Vishal Saxena
2022	C	`conf`	A Hybrid CMOS Photonic 25Gbps Microring Transmitter with a -0.5-1.2V Direct-Coupled Drive. ISCAS Shubham Mishra, Md Jubayer Shawon, Anuar Dorzhigulov, Vishal Saxena
2022	C	`conf`	Hybrid CMOS-RRAM Spiking CNNs with Time-Domain Max-pooling and Integrator Re-use. ISCAS Anuar Dorzhigulov, Shubham Mishra, Vishal Saxena
2021	C	`conf`	A Mixed-Signal Convolutional Neural Network Using Hybrid CMOS-RRAM Circuits. ISCAS Vishal Saxena
2021	J	`jnl`	Analysis of Trade-offs in RF Photonic Links based on Multi-Bias Tuning of Silicon Photonic Ring-Assisted Mach Zehnder Modulators. CoRR Md Jubayer Shawon, Vishal Saxena
2021	J	`jnl`	Mixed-Signal Neuromorphic Computing Circuits Using Hybrid CMOS-RRAM Integration. IEEE Trans. Circuits Syst. II Express Briefs Vishal Saxena
2020	J	`jnl`	A Deep Unsupervised Feature Learning Spiking Neural Network with Binarized Classification Layers for EMNIST Classification. CoRR Ruthvik Vaila, John N. Chiasson, Vishal Saxena
2020	C	`conf`	A Process-Variation Robust RRAM-Compatible CMOS Neuron for Neuromorphic System-on-a-Chip. ISCAS Vishal Saxena
2020	—	`conf`	Analysis of RF Photonic Link using Silicon Photonic Ring-Assisted Mach Zehnder Modulator. MWSCAS Md Jubayer Shawon, Vishal Saxena
2020	—	`conf`	Continuous Learning in a Single-Incremental-Task Scenario with Spike Features. ICONS Ruthvik Vaila, John N. Chiasson, Vishal Saxena
2020	J	`jnl`	Continuous Learning in a Single-Incremental-Task Scenario with Spike Features. CoRR Ruthvik Vaila, John N. Chiasson, Vishal Saxena
2020	J	`jnl`	Rapid Simulation of Photonic Integrated Circuits Using Verilog-A Compact Models. IEEE Trans. Circuits Syst. Md Jubayer Shawon, Vishal Saxena
2019	—	`conf`	A CMOS Photonic Optical PAM4 Transmitter Linearized using Three-Segment Ring Modulator. MWSCAS Rui Wang, Vishal Saxena
2019	J	`jnl`	Deep Convolutional Spiking Neural Networks for Image Classification. CoRR Ruthvik Vaila, John N. Chiasson, Vishal Saxena
2019	—	`conf`	Feature Extraction using Spiking Convolutional Neural Networks. ICONS Ruthvik Vaila, John N. Chiasson, Vishal Saxena
2019	—	`conf`	High LRS-Resistance CMOS Memristive Synapses for Energy-Efficient Neuromorphic SoCs. MWSCAS Vishal Saxena
2019	—	`conf`	Rapid Simulation of Photonic Integrated Circuits using Verilog-A Compact Models. MWSCAS Md Jubayer Shawon, Vishal Saxena
2018	—	`conf`	A 3D-Integrated 56 Gb/s NRZ/PAM4 Reconfigurable Segmented Mach-Zehnder Modulator-Based Si-Photonics Transmitter. BCICTS Cheng Li, Kunzhi Yu, Jinsoo Rhim, Kehan Zhu, Nan Qi, Marco Fiorentino, Thierry Pinguet, Mark Peterson, Vishal Saxena, Samuel Palermo
2018	—	`conf`	A Compact CMOS Memristor Emulator Circuit and its Applications. MWSCAS Vishal Saxena
2018	J	`jnl`	Dendritic-Inspired Processing Enables Bio-Plausible STDP in Compound Binary Synapses. CoRR Xinyu Wu, Vishal Saxena
2018	—	`conf`	Design and Compact Modeling of Silicon-Photonic Coupling-Based Ring Modulators for Optical Interconnects. MWSCAS Rui Wang, Md Jubayer Shawon, Vishal Saxena
2018	—	`conf`	Design and Modeling of Silicon Photonic Ring-Based Linearized RF-to-Optical Modulator. MWSCAS Md Jubayer Shawon, Rui Wang, Vishal Saxena
2018	C	`conf`	Energy-Efficient CMOS Memristive Synapses for Mixed-Signal Neuromorphic System-on-a-Chip. ISCAS Vishal Saxena, Xinyu Wu, Kehan Zhu
2018	J	`jnl`	Energy-Efficient CMOS Memristive Synapses for Mixed-Signal Neuromorphic System-on-a-Chip. CoRR Vishal Saxena, Xinyu Wu, Kehan Zhu
2018	J	`jnl`	From Design to Test: A High-Speed PRBS. IEEE Trans. Very Large Scale Integr. Syst. Kehan Zhu, Vishal Saxena
2017	J	`jnl`	A Compact CMOS Memristor Emulator Circuit and its Applications. CoRR Vishal Saxena
2017	—	`conf`	Behavioral modeling and characterization of silicon photonic Mach-Zehnder modulator. MWSCAS Kehan Zhu, Rui Wang, Xinyu Wu, Vishal Saxena
2017	J	`jnl`	Case Study of a Hybrid Optoelectronic Limiting Receiver. IEEE Trans. Circuits Syst. I Regul. Pap. Kehan Zhu, Vishal Saxena
2017	B	`conf`	Enabling bio-plausible multi-level STDP using CMOS neurons with dendrites and bistable RRAMs. IJCNN Xinyu Wu, Vishal Saxena
2017	C	`conf`	Realization of a 10 GHz PLL in IBM 130 nm SiGe BiCMOS process for optical transmitter. ISCAS Kehan Zhu, Sakkarapani Balagopal, Xinyu Wu, Vishal Saxena
2017	—	`conf`	Towards spiking neuromorphic system-on-a-chip with bio-plausible synapses using emerging devices. NANOCOM Vishal Saxena, Xinyu Wu, Ira Srivastava, Kehan Zhu
2016	J	`jnl`	Enabling Bio-Plausible Multi-level STDP using CMOS Neurons with Dendrites and Bistable RRAMs. CoRR Xinyu Wu, Vishal Saxena
2016	—	`conf`	Modeling and optimization of the bond-wire interface in a Hybrid CMOS-photonic traveling-wave MZM transmitter. SoCC Kehan Zhu, Vishal Saxena, Xinyu Wu
2016	—	`conf`	Tutorial 4B: ADC design - from system architecture to transistor level design. SoCC Bhibhudatta Sahoo, Vishal Saxena, Karan S. Bhatia
2015	J	`jnl`	A CMOS Spiking Neuron for Brain-Inspired Neural Networks With Resistive Synapses and In Situ Learning. IEEE Trans. Circuits Syst. II Express Briefs Xinyu Wu, Vishal Saxena, Kehan Zhu, Sakkarapani Balagopal
2015	J	`jnl`	A CMOS Spiking Neuron for Brain-Inspired Neural Networks with Resistive Synapses and In-Situ Learning. CoRR Xinyu Wu, Vishal Saxena, Kehan Zhu, Sakkarapani Balagopal
2015	J	`jnl`	A CMOS Spiking Neuron for Dense Memristor-Synapse Connectivity for Brain-Inspired Computing. CoRR Xinyu Wu, Vishal Saxena, Kehan Zhu
2015	B	`conf`	A CMOS spiking neuron for dense memristor-synapse connectivity for brain-inspired computing. IJCNN Xinyu Wu, Vishal Saxena, Kehan Zhu
2015	—	`conf`	A comprehensive design approach for a MZM based PAM-4 silicon photonic transmitter. MWSCAS Kehan Zhu, Vishal Saxena, Xinyu Wu
2015	J	`jnl`	Design Considerations for Traveling-Wave Modulator-Based CMOS Photonic Transmitters. IEEE Trans. Circuits Syst. II Express Briefs Kehan Zhu, Vishal Saxena, Xinyu Wu, Wan Kuang
2015	J	`jnl`	Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition. CoRR Xinyu Wu, Vishal Saxena, Kehan Zhu
2015	J	`jnl`	Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition. IEEE J. Emerg. Sel. Topics Circuits Syst. Xinyu Wu, Vishal Saxena, Kehan Zhu
2014	—	`conf`	Compact Verilog-A modeling of silicon traveling-wave modulator for hybrid CMOS photonic circuit design. MWSCAS Kehan Zhu, Vishal Saxena, Wan Kuang
2013	—	`conf`	Design of a 10-Gb/s integrated limiting receiver for silicon photonics interconnects. MWSCAS Kehan Zhu, Sakkarapani Balagopal, Vishal Saxena, Wan Kuang
2013	—	`conf`	Systematic synthesis of cascaded continuous-time ΔΣ ADCs for wideband data conversion. MWSCAS Sakkarapani Balagopal, Kehan Zhu, Vishal Saxena
2012	—	`conf`	A 1 GS/s, 31 MHz BW, 76.3 dB dynamic range, 34 mW CT-ΔΣ ADC with 1.5 cycle quantizer delay and improved STF. MWSCAS Sakkarapani Balagopal, Vishal Saxena
2012	—	`conf`	Design of wideband continuous-time ΔΣ ADCs using two-step quantizers. MWSCAS Sakkarapani Balagopal, Vishal Saxena
2011	—	`conf`	Efficient design and synthesis of decimation filters for wideband delta-sigma ADCs. SoCC Rajaram Mohan Roy Koppula, Sakkarapani Balagopal, Vishal Saxena
2005	—	`conf`	A Non-invasive, Multi-modality Approach Based on NIRS and MRI Techniques For Monitoring Intracranial Brain Tumor Angiogenesis. AIPR Vishal Saxena, Jon-Fredrik Nielsen, Ignacio Gonzalez-Gomez, Gevorg Karapetyan, Vazgen Khankaldyyan, Marvin D. Nelson Jr., Walter E. Laug