Vishal Khandelwal

31 papers A* 3A 8C 1Misc 2Journal 8Unranked 7

Year	Rank	Type	Title / Venue / Authors
2023	A*	`conf`	RL-CCD: Concurrent Clock and Data Optimization using Attention-Based Self-Supervised Reinforcement Learning. DAC Yi-Chen Lu, Wei-Ting Chan, Deyuan Guo, Sudipto Kundu, Vishal Khandelwal, Sung Kyu Lim
2022	—	`conf`	Driving Early Physical Synthesis Exploration through End-of-Flow Total Power Prediction. MLCAD Yi-Chen Lu, Wei-Ting Chan, Vishal Khandelwal, Sung Kyu Lim
2022	—	`conf`	Machine-Learning Enabled PPA Closure for Next-Generation Designs. ISPD Vishal Khandelwal
2021	A	`conf`	Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning. ICCAD Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim
2021	—	`conf`	Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation At Advanced Process Nodes. ISPD Siddhartha Nath, Vishal Khandelwal
2021	A*	`conf`	RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning. DAC Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim
2020	—	`conf`	Machine-Learning Enabled Next-Generation Physical Design - An EDA Perspective. MLCAD Vishal Khandelwal
2009	—	`conf`	On improving optimization effectiveness in interconnect-driven physical synthesis. ISPD Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin, Mahesh A. Iyer
2008	—	`ch.`	Basic Algorithmic Techniques. Handbook of Algorithms for Physical Design Automation Vishal Khandelwal, Ankur Srivastava
2008	J	`jnl`	Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vishal Khandelwal, Ankur Srivastava
2007	J	`jnl`	A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations. IEEE Trans. Very Large Scale Integr. Syst. Vishal Khandelwal, Ankur Srivastava
2007	J	`jnl`	Active mode leakage reduction using fine-grained forward body biasing strategy. Integr. Vishal Khandelwal, Ankur Srivastava
2007	Misc	`conf`	Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental Attributes. VLSI Design Ashish Dobhal, Vishal Khandelwal, Ankur Srivastava
2007	J	`jnl`	Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vishal Khandelwal, Ankur Srivastava
2007	A	`conf`	Monte-Carlo driven stochastic optimization framework for handling fabrication variability. ICCAD Vishal Khandelwal, Ankur Srivastava
2007	C	`conf`	Statistical timing analysis using Kernel smoothing. ICCD Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak
2007	Misc	`conf`	Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence. VLSI Design Ashish Dobhal, Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava
2007	—	`—`	Variability-Aware VLSI Design Automation For Nanoscale Technologies. Vishal Khandelwal
2007	—	`conf`	Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation. ISPD Vishal Khandelwal, Ankur Srivastava
2006	J	`jnl`	A statistical methodology for wire-length prediction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak
2006	J	`jnl`	Probabilistic Evaluation of Solutions in Variability-Driven Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
2005	A*	`conf`	A general framework for accurate statistical timing analysis considering correlations. DAC Vishal Khandelwal, Ankur Srivastava
2005	J	`jnl`	Simultaneous V IEEE Trans. Very Large Scale Integr. Syst. Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava
2004	A	`conf`	Active mode leakage reduction using fine-grained forward body biasing strategy. ISLPED Vishal Khandelwal, Ankur Srivastava
2004	A	`conf`	Efficient statistical timing analysis through error budgeting. ICCAD Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava
2004	J	`jnl`	Empirical models for net-length probability distribution and applications. IEEE Trans. Very Large Scale Integr. Syst. Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
2004	—	`conf`	High level techniques for power-grid noise immunity. ACM Great Lakes Symposium on VLSI Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
2004	A	`conf`	Leakage control through fine-grained placement and sizing of sleep transistors. ICCAD Vishal Khandelwal, Ankur Srivastava
2004	A	`conf`	Variability inspired implementation selection problem. ICCAD Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
2004	A	`conf`	Wire-length prediction using statistical techniques. ICCAD Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak
2003	A	`conf`	A Probabilistic Approach to Buffer Insertion. ICCAD Vishal Khandelwal, Azadeh Davoodi, Akash Nanavati, Ankur Srivastava