Viresh Paruthi

21 papers A* 3A 2B 6C 3Journal 5Unranked 2
YearRankTypeTitle / Venue / Authors
2025 J jnl
Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization.
CoRR
Prashanth Vijayaraghavan, Apoorva Nitsure, Charles Mackin, Luyao Shi, Stefano Ambrogio, Arvind Haran, Viresh Paruthi, Ali El-Zein, Dan Coops, David Beymer, Tyler Baldwin, Ehsan Degan
2024 — conf
Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization.
MLCAD
Prashanth Vijayaraghavan, Apoorva Nitsure, Charles Mackin, Luyao Shi, Stefano Ambrogio, Arvind Haran, Viresh Paruthi, Ali El-Zein, Dan Coops, David Beymer, Tyler Baldwin, Ehsan Degan
2015 A conf
Designer-level verification: an industrial experience story.
DATE
Stephen Bergman, Gabor Bobok, Walter Kowalski, Shlomit Koyfman, Shiri Moran, Ziv Nevo, Avigail Orni, Viresh Paruthi, Wolfgang Roesner, Gil Shurek, Vasantha Vuyyuru
2015 J jnl
Solutions to IBM POWER8 verification challenges.
IBM J. Res. Dev.
Klaus-Dieter Schubert, John M. Ludden, Salma Ayub, J. Behrend, Bishop Brock, Fady Copty, S. M. German, Oz Hershkovitz, H. Horbach, Jonathan R. Jackson, K. Keuerleber, J. Koesters, Larry S. Leitner, G. B. Meil, Charles Meissner, Ronny Morad, Amir Nahir, Viresh Paruthi, Richard D. Peterson, Randall R. Pratt, Michal Rimon, John Schumann
2014 A* conf
Automatic Verification of Floating Point Units.
DAC
Udo Krautz, Viresh Paruthi, Anand Arunagiri, Sujeet Kumar, Shweta Pujar, Tina Babinsky
2014 J jnl
Verification of Galois field based circuits by formal reasoning based on computational algebraic geometry.
Formal Methods Syst. Des.
Alexey Lvov, Luis Alfonso Lastras-Montaño, Barry M. Trager, Viresh Paruthi, Robert Shadowen, Ali El-Zein
2012 B conf
Formal verification of error correcting circuits using computational algebraic geometry.
FMCAD
Alexey Lvov, Luis Alfonso Lastras-Montaño, Viresh Paruthi, Robert Shadowen, Ali El-Zein
2011 B conf
Hybrid verification of a hardware modular reduction engine.
FMCAD
Jun Sawada, Peter Sandon, Viresh Paruthi, Jason Baumgartner, Michael L. Case, Hari Mony
2010 B conf
Formal verification of arbiters using property strengthening and underapproximations.
FMCAD
Gadiel Auerbach, Fady Copty, Viresh Paruthi
2010 B conf
Large-scale application of formal verification: From fiction to fact.
FMCAD
Viresh Paruthi
2009 B conf
Formal verification of correctness and performance of random priority-based arbiters.
FMCAD
Krishnan Kailas, Viresh Paruthi, Brian Monwai
2006 C conf
Scalable Sequential Equivalence Checking across Arbitrary Design Transformations .
ICCD
Jason Baumgartner, Hari Mony, Viresh Paruthi, Robert Kanzelman, Geert Janssen
2005 A conf
Automatic Formal Verification of Fused-Multiply-Add FPUs.
DATE
Christian Jacobi, Kai Weber, Viresh Paruthi, Jason Baumgartner
2005 — conf
Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting.
CHARME
Viresh Paruthi, Christian Jacobi, Kai Weber
2005 A* conf
Exploiting suspected redundancy without proving it.
DAC
Hari Mony, Jason Baumgartner, Viresh Paruthi, Robert Kanzelman
2004 B conf
Scalable Automated Verification via Expert-System Guided Transformations.
FMCAD
Hari Mony, Jason Baumgartner, Viresh Paruthi, Robert Kanzelman, Andreas Kuehlmann
2002 J jnl
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system.
IBM J. Res. Dev.
John M. Ludden, Wolfgang Roesner, Gerry M. Heiling, John R. Reysa, Jonathan R. Jackson, Bing-Lun Chu, Michael L. Behm, Jason Baumgartner, Richard D. Peterson, Jamee Abdulhafiz, William E. Bucy, John H. Klaus, Danny J. Klema, Tien N. Le, F. Danette Lewis, Philip E. Milling, Lawrence A. McConville, Bradley S. Nelson, Viresh Paruthi, Travis W. Pouarz, Audre D. Romonosky, Jeff Stuecheli, Kent D. Thompson, Dave W. Victor, Bruce Wile
2002 J jnl
Robust Boolean reasoning for equivalence checking and functional property verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, Malay K. Ganai
2001 A* conf
Circuit-based Boolean Reasoning.
DAC
Andreas Kuehlmann, Malay K. Ganai, Viresh Paruthi
2000 C conf
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation.
ICCD
Viresh Paruthi, Andreas Kuehlmann
1998 C conf
Automatic data path abstraction for verification of large scale designs.
ICCD
Viresh Paruthi, Nazanin Mansouri, Ranga Vemuri