Virendra Singh

195 papers A 6B 6C 41Misc 19Journal 27Unranked 91

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	DREAM: Dynamic, Reinforced, and Evasive Attack Model on Spatio-Temporal GNNs. ICAART (3) Mandru Suma Sri, Uddhav Narayan Gilda, Tarun Bisht, Virendra Singh
2026	—	`conf`	LA-SCG: Layout-Aware Scan Chain Grouping for Peak Shift Power and IR-Drop Mitigation in Scan-Based Testing. LATS Rohit Badjatya, Harsh Gupta, Makoto Ikeda, Masahiro Fujita, Virendra Singh
2026	—	`conf`	LPCG: A Capture Activity-Aware Technique for Low-Power Scan Testing. LATS Rohit Badjatya, Jaydev Bapat, Makoto Ikeda, Masahiro Fujita, Virendra Singh
2026	—	`conf`	Sparse Rewards as Preferences: Investigating Reward Shaping with Preference-Based RL Methods in Sparse Reward Domains. ICAART (1) Veerendrababu Vakkapatla, Shariq Faraz, Virendra Singh
2026	J	`jnl`	Toxicbias-reasoning: a multicultural dataset for social bias detection with human-aligned reasoning. Lang. Resour. Evaluation Anuj Kumar, Mahendra Kumar Gurve, Satyadev Ahlawat, Yamuna Prasad, Virendra Singh
2025	C	`conf`	A New Hardware Trojan Attack on Scan-obfuscated Logic-locked Circuits. ISCAS Anjum Riaz, Gaurav Kumar, Yamuna Prasad, Satyadev Ahlawat, Virendra Singh
2025	J	`jnl`	B-CAVE: A Robust Online Time Series Change Point Detection Algorithm Based on the Between-Class Average and Variance Evaluation Approach. IEEE Trans. Knowl. Data Eng. Aditi Gupta, Adeiza James Onumanyi, Satyadev Ahlawat, Yamuna Prasad, Virendra Singh
2025	C	`conf`	EDQKD: Enhanced-Dynamic Quantum Key Distributions with Improved Security and Key Rate. SECRYPT Nikhil Kumar Parida, Sarath Babu, Neeraj Panwar, Virendra Singh
2025	J	`jnl`	Enhancing Healthcare Data Privacy in Cloud IoT Networks Using Anomaly Detection and Optimization with Explainable AI (ExAI). Comput. Mater. Continua Jitendra Kumar Samriya, Virendra Singh, Gourav Bathla, Meena Malik, Varsha Arya, Wadee Alhalabi, Brij B. Gupta
2025	C	`conf`	GPD: Predictive Control Flow Error Detection Leveraging Data Flow Error Detection Methods. IOLTS Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh
2025	C	`conf`	LiC: Low-Cost Cache Replacement Algorithm for All Cache Levels. VLSI-SoC Varun Venkitaraman, Tejeshwar Bhagatsing Thorawade, Mitul Tandon, Keerthisagar Kokkiligadda, Virendra Singh, Janak Patel
2025	Misc	`conf`	Lichen: Leveraging Coupled Heterogeneity. VLSID Prakhar Diwan, Nirmal Kumar Boran, Virendra Singh
2025	—	`conf`	On Enhancing the Security Against Memory Disclosure Attacks. SOCC Prokash Ghosh, Gaurav Kumar, Sohan Lal, Satyadev Ahlawat, Virendra Singh
2025	C	`conf`	RRR: Robust runtime reconfigurable shared cache management scheme for GPGPUs. ISCAS Varun Venkitaraman, Shrasti Bhargava, Tejeshwar Bhagatsing Thorawade, Keerthisagar Kokkiligadda, Rahul Kumar, Virendra Singh
2025	C	`conf`	SCAM: Secure Shared Cache Partitioning Scheme to Enhance Throughput of CMPs. SECRYPT Varun Venkitaraman, Rishab Ravi, Tejeshwar Bhagatsing Thorawade, Nirmal Kumar Boran, Virendra Singh
2025	C	`conf`	Stegoslayer: A Robust Browser-Integrated Approach for Thwarting Stegomalware. SECRYPT Rushikesh Kawale, Sarath Babu, Virendra Singh
2025	C	`conf`	TRAP: Time-Aware Probabilistic In-Dram RowHammer Solution. SBAC-PAD Samiksha Verma, Virendra Singh
2025	A	`conf`	Test Data Compaction Techniques with Improved Diagnostic Capabilities and Reduced Tester Time. ITC Jaidev Shenoy, Virendra Singh, Kelly Ockunzzi
2025	—	`conf`	Video-guided Machine Translation: A Survey of Models, Datasets, and Challenges. IJCNLP-AACL (long papers) Pinaki Das, Virendra Singh, Pushpak Bhattacharyya, Gholamreza Haffari
2025	—	`conf`	Weight-Aware Scan Chain Stitching for Shift Power Minimization under Routing Constraints. ATS Rohit Badjatya, Kapil Sharma, Makoto Ikeda, Masahiro Fujita, Virendra Singh
2024	J	`jnl`	A-TSPD: autonomous-two stage algorithm for robust peak detection in online time series. Clust. Comput. Aditi Gupta, Sukanya Gupta, Adeiza James Onumanyi, Satyadev Ahlawat, Yamuna Prasad, Virendra Singh
2024	J	`jnl`	Accelerating Neural Network Inference in Handwritten Digit Recognition - Comparative Study. Parallel Process. Lett. Winnie Thomas, Virendra Singh
2024	J	`jnl`	BD-MDLC: Behavior description-based enhanced malware detection for windows environment using longformer classifier. Comput. Secur. Sarath Babu, Virendra Singh
2024	C	`conf`	Critical Behavior Sequence Monitoring for Early Malware Detection. SIN Tarun Bisht, Sarath Babu, Virendra Singh
2024	J	`jnl`	DAT: A robust Discriminant Analysis-based Test of unimodality for unknown input distributions. Pattern Recognit. Lett. Aditi Gupta, Adeiza James Onumanyi, Satyadev Ahlawat, Yamuna Prasad, Virendra Singh, Adnan M. Abu-Mahfouz
2024	Misc	`conf`	Early Execution for Soft Error Detection. VLSID Raj Kumar Choudhary, Janeel Patel, Virendra Singh
2024	—	`conf`	GNNDLD: Graph Neural Network with Directional Label Distribution. ICAART (2) Chandramani Chaudhary, Nirmal Kumar Boran, N. Sangeeth, Virendra Singh
2024	Misc	`conf`	MALAI: ML-Based Attack on Learning with Error Problem. ICISS Mandru Suma Sri, Chakka Srikanth Yadav, Tikaram Sanyashi, Virendra Singh
2024	Misc	`conf`	MIST: Many-ISA Scheduling Technique for Heterogeneous-ISA Architectures. VLSID Prakhar Diwan, Suryakant Toraskar, Varun Venkitaraman, Nirmal Kumar Boran, Chandramani Chaudhary, Virendra Singh
2024	—	`conf`	Physical-Design Aware Scan Cell Reordering for Low Power Testing. EWDTS Rohit Badjatya, N. S. Vinay, Rahul Kumar, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh
2024	C	`conf`	S-Clflush: Securing Against Flush-based Cache Timing Side-Channel Attacks. SBAC-PAD Tejeshwar Bhagatsing Thorawade, Prajakta Yeola, Varun Venkitaraman, Virendra Singh
2024	—	`conf`	SMS: Solving Many-sided RowHammer. MEMSYS Samiksha Verma, Virendra Singh
2024	J	`jnl`	Security in 5G Network Slices: Concerns and Opportunities. IEEE Access Virendra Singh, Mahendra Pratap Singh, Saumya Hegde, Maanak Gupta
2024	C	`conf`	TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error Detection. DDECS Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh
2024	—	`conf`	TRRR: Accelerated Online Error Detecting and Correcting Fault Tolerant Architecture. EWDTS Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh
2023	—	`conf`	DDSR: An Online GPGPU Instruction Decoder Error Detecting and Correcting Architecture. DFT Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh
2023	C	`conf`	ERrOR: Improving Performance and Fault Tolerance Using Early Execution. IOLTS Raj Kumar Choudhary, Janeel Patel, Virendra Singh
2023	—	`conf`	LUT-based Arithmetic Circuit Approximation with Formal Guarantee on Worst Case Relative Error. LATS Pooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh
2023	—	`conf`	On Attacking Scan-based Logic Locking Schemes. DFT Govind Rajhans Jadhav, Sonali Shukla, Virendra Singh
2023	C	`conf`	On-Chip SRAM Disclosure Attack Prevention Technique for SoC. IOLTS Prokash Ghosh, Yogesh Gholap, Virendra Singh
2023	—	`conf`	Optimization of Imprecise Multiplier Circuits by using Binary Decision Diagram. iSES Pooja Choudhary, Lava Bhargava, G. U. Vinod, Ashok Kumar Suhag, Masahiro Fujita, Virendra Singh
2023	—	`conf`	SMASh: A State Encoding Methodology Against Attacks on Finite State Machines. ATS Gowthami Konganapalle, Sonali Shukla, Virendra Singh
2023	—	`conf`	SSSN: Secured Streaming Scan Network. LATS Sonali Shukla, Bhavika Ranjeet Kumar, Virendra Singh
2023	Misc	`conf`	Secure KNN Computation on Cloud. ICISS Tikaram Sanyashi, Nirmal Kumar Boran, Virendra Singh
2023	C	`conf`	TREFU: An Online Error Detecting and Correcting Fault Tolerant GPGPU Architecture. IOLTS Raghunandana K. K, B. K. S. V. L. Varaprasad, Matteo Sonza Reorda, Virendra Singh
2023	—	`conf`	TSPD: A Robust Online Time Series Two-Stage Peak Detection Algorithm. SOSE Aditi Gupta, Adeiza James Onumanyi, Satyadev Ahlawat, Yamuna Prasad, Virendra Singh
2022	J	`jnl`	Approximating Arithmetic Circuits for IoT Devices Data Processing. Comput. Ind. Eng. Pooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh, Ashok Kumar Suhag
2022	—	`conf`	Disrupting Low-Write-Energy vs. Fast-Read Dilemma in RRAM to Enable L1 Instruction Cache. VDAT Ashwin Sanjay Lele, Srivatsava Jandhyala, Saurabh Gangurde, Virendra Singh, Sreenivas Subramoney, Udayan Ganguly
2022	Misc	`conf`	Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries. VTS Riccardo Cantoro, Francesco Garau, Riccardo Masante, Sandro Sartoni, Virendra Singh, Matteo Sonza Reorda
2022	C	`conf`	PASS-P: Performance and Security Sensitive Dynamic Cache Partitioning. SECRYPT Nirmal Kumar Boran, Pranil Joshi, Virendra Singh
2022	—	`conf`	REFU: Redundant Execution with Idle Functional Units, Fault Tolerant GPGPU architecture. ISVLSI Raghunandana K. K, B. K. S. V. L. Varaprasad, Matteo Sonza Reorda, Virendra Singh
2022	—	`conf`	Scalable Construction of Formal Error Guaranteed LUT-Based Approximate Multipliers with Analytical Worst-Case Error Bound. VDAT Anishetti Venkatesh, Chandan Kumar Jha, G. U. Vinod, Masahiro Fujita, Virendra Singh
2022	—	`conf`	Synthesis of LUT Based Approximating Adder Circuits with Formal Error Guarantees. VDAT Pooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh
2021	J	`jnl`	A Framework for Configurable Joint-Scan Design-for-Test Architecture. J. Electron. Test. Jaynarayan T. Tudu, Satyadev Ahlawat, Sonali Shukla, Virendra Singh
2021	J	`jnl`	DAM: Deadblock Aware Migration Techniques for STT-RAM-Based Hybrid Caches. IEEE Comput. Archit. Lett. Arindam Sarkar, Newton Singh, Varun Venkitaraman, Virendra Singh
2021	C	`conf`	Dynamic Optimizations in GPU Using Roofline Model. ISCAS Winnie Thomas, Suryakant Toraskar, Virendra Singh
2021	J	`jnl`	Enhanced Design Debugging With Assistance From Guidance-Based Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. V. S. Vineesh, Binod Kumar, Rushikesh Shinde, Neelam Sharma, Masahiro Fujita, Virendra Singh
2021	—	`conf`	Enhancing Testbench Quality via Genetic Algorithm. MWSCAS Harsh Bhargav, Vineesh V. S., Binod Kumar, Virendra Singh
2021	J	`jnl`	Fine-Grained Scheduling in Heterogeneous-ISA Architectures. IEEE Comput. Archit. Lett. Nirmal Kumar Boran, Shubhankit Rathore, Meet Udeshi, Virendra Singh
2021	J	`jnl`	Locality-based Graph Reordering for Processing Speed-Ups and Impact of Diameter. CoRR Vedant Satav, Virendra Singh
2021	—	`conf`	Predictive Warp Scheduling for Efficient Execution in GPGPU. ACM Great Lakes Symposium on VLSI Abhinish Anand, Winnie Thomas, Suryakant Toraskar, Virendra Singh
2021	—	`conf`	Secrecy Rate Maximization at Near User in Untrusted NOMA with Trusted DF Relay. ANTS Insha Amin, Deepak Mishra, Ravikant Saini, Virendra Singh
2020	Misc	`conf`	A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors. VLSID Binod Kumar, Swapniel Thakur, Kanad Basu, Masahiro Fujita, Virendra Singh
2020	J	`jnl`	A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. Binod Kumar, Jay Adhaduk, Kanad Basu, Masahiro Fujita, Virendra Singh
2020	B	`conf`	Characterization of Data Generating Neural Network Applications on x86 CPU Architecture. ISPASS Antara Ganguly, Shankar Balachandran, Anant V. Nori, Virendra Singh, Sreenivas Subramoney
2020	—	`conf`	LUT-based Circuit Approximation with Targeted Error Guarantees. ATS Vinod G. U, Vineesh V. S., Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh
2020	J	`jnl`	PIM-GraphSCC: PIM-Based Graph Processing Using Graph's Community Structures. IEEE Comput. Archit. Lett. Newton, Virendra Singh, Trevor E. Carlson
2020	J	`jnl`	Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Binod Kumar, Kanad Basu, Masahiro Fujita, Virendra Singh
2019	Misc	`conf`	A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation. VLSID Binod Kumar, Masahiro Fujita, Virendra Singh
2019	C	`conf`	Freeflow Core: Enhancing Performance of In-Order Cores with Energy Efficiency. ICCD Raj Kumar Choudhary, Newton Singh, Harideep Nair, Rishabh Rawat, Virendra Singh
2019	Misc	`conf`	On-chip MISR Compaction Technique to Reduce Diagnostic Effort and Test Time. VLSID Jaidev Shenoy, Kelly Ockunzzi, Virendra Singh, Kushal Kamal
2019	—	`conf`	Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification. ATS Vineesh V. S., Binod Kumar, Rushikesh Shinde, Akshay Jaiswal, Harsh Bhargava, Virendra Singh
2019	—	`conf`	Preventing Scan Attack through Test Response Encryption. DFT Satyadev Ahlawat, Jaynarayan T. Tudu, Manoj Singh Gaur, Masahiro Fujita, Virendra Singh
2019	J	`jnl`	SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement. J. Electron. Test. Binod Kumar, Masahiro Fujita, Virendra Singh
2019	C	`conf`	Securing Scan through Plain-text Restriction. IOLTS Satyadev Ahlawat, Kailash Ahirwar, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh
2019	—	`ed.`	Security and Privacy - Second ISEA International Conference, ISEA-ISAP 2018, Jaipur, India, January, 9-11, 2019, Revised Selected Papers ISEA-ISAP Sukumar Nandi, Devesh Jinwala, Virendra Singh, Vijay Laxmi, Manoj Singh Gaur, Parvez Faruki
2019	J	`jnl`	Soft-error reliable architecture for future microprocessors. IET Comput. Digit. Tech. Shoba Gopalakrishnan, Virendra Singh
2019	—	`conf`	Towards Energy Efficient non-von Neumann Architectures for Deep Learning. ISQED Antara Ganguly, Rajeev Muralidhar, Virendra Singh
2019	—	`ed.`	VLSI Design and Test - 22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised Selected Papers VDAT S. Rajaram, N. B. Balamurugan, D. Gracia Nirmala Rani, Virendra Singh
2019	—	`ed.`	VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers VDAT Anirban Sengupta, Sudeb Dasgupta, Virendra Singh, Rohit Sharma, Santosh Kumar Vishvakarma
2019	—	`conf`	Validating Multi-Processor Cache Coherence Mechanisms under Diminished Observability. ATS Binod Kumar, Atul Kumar Bhosale, Masahiro Fujita, Virendra Singh
2018	C	`conf`	A PAM-4 10S/12S line coding scheme with equi-probable levels. ISCAS Sandeep Goyal, Ron Joseph, Virendra Singh, Shalabh Gupta
2018	—	`conf`	A Technique for Electrical Error Localization with Learning Methods During Post-silicon Debugging. IGSC Binod Kumar, Kanad Basu, Virendra Singh
2018	—	`conf`	AB-Aware: Application Behavior Aware Management of Shared Last Level Caches. ACM Great Lakes Symposium on VLSI Suhit Pai, Newton Singh, Virendra Singh
2018	A	`conf`	ATPG power guards: On limiting the test power below threshold. DATE Rohini Gulve, Virendra Singh
2018	C	`conf`	In-situ Monitoring for Slack Time Violation Without Performance Penalty. ISCAS Nihar Hage, Satyadev Ahlawat, Virendra Singh
2018	—	`conf`	Memory-system requirements for convolutional neural networks. MEMSYS Antara Ganguly, Virendra Singh, Rajeev Muralidhar, Masahiro Fujita
2018	J	`jnl`	Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design. J. Electron. Test. Toral Shah, Anzhela Yu. Matrosova, Masahiro Fujita, Virendra Singh
2018	C	`conf`	On Securing Scan Design Through Test Vector Encryption. ISCAS Darshit Vaghani, Satyadev Ahlawat, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh
2018	—	`conf`	Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm. ISVLSI Ankit Jindal, Binod Kumar, Nitish Jindal, Masahiro Fujita, Virendra Singh
2018	—	`conf`	Using MISR as Countermeasure Against Scan-Based Side-Channel Attacks. EWDTS Satyadev Ahlawat, Darshit Vaghani, Naveen Bazard, Virendra Singh
2017	Misc	`conf`	A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation. VLSID Binod Kumar, Ankit Jindal, Virendra Singh, Masahiro Fujita
2017	J	`jnl`	A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging. J. Electron. Test. Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja
2017	C	`conf`	A low cost technique for scan chain diagnosis. ISCAS Satyadev Ahlawat, Darshit Vaghani, Rohini Gulve, Virendra Singh
2017	—	`conf`	Achieving full functional coverage for the forwarding unit of pipelined processors. EWDTS V. S. Vineesh, Nihar Hage, B. Karthik, Virendra Singh
2017	B	`conf`	An efficient test technique to prevent scan-based side-channel attacks. ETS Satyadev Ahlawat, Darshit Vaghani, Virendra Singh
2017	—	`conf`	Combining Restorability and Error Detection Ability for Effective Trace Signal Selection. ACM Great Lakes Symposium on VLSI Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh
2017	C	`conf`	DAAIP: Deadblock Aware Adaptive Insertion Policy for High Performance Caching. ICCD Newton, Sujit Kr Mahto, Suhit Pai, Virendra Singh
2017	—	`conf`	EEAL: Processors' Performance Enhancement Through Early Execution of Aliased Loads. ACM Great Lakes Symposium on VLSI Abhishek Rajgadia, Newton, Virendra Singh
2017	A	`conf`	Exploiting path delay test generation to develop better TDF tests for small delay defects. ITC Ankush Srivastava, Adit D. Singh, Virendra Singh, Kewal K. Saluja
2017	—	`conf`	Identifying high variability speed-limiting paths under aging. LATS Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja
2017	C	`conf`	Improving post-silicon error detection with topological selection of trace signals. VLSI-SoC Binod Kumar, Kanad Basu, Ankit Jindal, Masahiro Fujita, Virendra Singh
2017	Misc	`ed.`	Information Systems Security - 13th International Conference, ICISS 2017, Mumbai, India, December 16-20, 2017, Proceedings ICISS Rudrapatna K. Shyamasundar, Virendra Singh, Jaideep Vaidya
2017	C	`conf`	Instruction-based self-test for delay faults maximizing operating temperature. IOLTS Nihar Hage, Rohini Gulve, Masahiro Fujita, Virendra Singh
2017	—	`conf`	On Securing Scan Design from Scan-Based Side-Channel Attacks. ATS Satyadev Ahlawat, Darshit Vaghani, Jaynarayan T. Tudu, Virendra Singh
2017	Misc	`conf`	On Testing of Superscalar Processors in Functional Mode for Delay Faults. VLSID Nihar Hage, Rohini Gulve, Masahiro Fujita, Virendra Singh
2017	—	`conf`	PHP: Power hungry pattern generation at higher abstraction level. EWDTS Rohini Gulve, Anshu Goel, Virendra Singh
2017	—	`conf`	Post-silicon observability enhancement with topology based trace signal selection. LATS Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh
2017	—	`conf`	Preventing scan-based side-channel attacks through key masking. DFT Satyadev Ahlawat, Darshit Vaghani, Virendra Singh
2017	—	`conf`	REMORA: A hybrid low-cost soft-error reliable fault tolerant architecture. DFT Shoba Gopalakrishnan, Virendra Singh
2017	—	`conf`	RTL level trace signal selection and coverage estimation during post-silicon validation. HLDVT Binod Kumar, Kanad Basu, Masahiro Fujita, Virendra Singh
2017	C	`conf`	Revisiting random access scan for effective enhancement of post-silicon observability. IOLTS Binod Kumar, Ankit Jindal, Jaynarayan T. Tudu, Brajesh Pandey, Virendra Singh
2017	C	`conf`	Test pattern generation to detect multiple faults in ROBDD based combinational circuits. IOLTS Toral Shah, Anzhela Yu. Matrosova, Virendra Singh
2017	—	`conf`	Testing multiple stuck-at faults of ROBDD based combinational circuit design. LATS Toral Shah, Anzhela Yu. Matrosova, Binod Kumar, Masahiro Fujita, Virendra Singh
2017	—	`ed.`	VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers VDAT Brajesh Kumar Kaushik, Sudeb Dasgupta, Virendra Singh
2016	C	`conf`	A high performance scan flip-flop design for serial and mixed mode scan test. IOLTS Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh
2016	—	`conf`	A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture. EWDTS Binod Kumar, Boda Nehru, Brajesh Pandey, Virendra Singh, Jaynarayan T. Tudu
2016	—	`conf`	A trace signal selection algorithm for improved post-silicon debug. EWDTS Binod Kumar, Ankit Jindal, Virendra Singh
2016	—	`conf`	Enabling LOS delay test with slow scan enable. EWDTS Satyadev Ahlawat, Darshit Vaghani, Rohini Gulve, Virendra Singh
2016	—	`conf`	ILP based don't care bits filling technique for reducing capture power. EWDTS Rohini Gulve, Virendra Singh
2016	—	`conf`	Performance modelling of heterogeneous ISA multicore architectures. EWDTS Nirmal Kumar Boran, Rameshwar Prasad Meghwal, Kuldeep Sharma, Binod Kumar, Virendra Singh
2016	C	`conf`	REMO: Redundant execution with minimum area, power, performance overhead fault tolerant architecture. IOLTS Shoba Gopalakrishnan, Virendra Singh
2016	—	`conf`	ROBDD based path delay fault testable combinational circuit synthesis. EWDTS Toral Shah, Virendra Singh, Anzhela Yu. Matrosova
2015	—	`conf`	A Methodology for Identifying High Timing Variability Paths in Complex Designs. ATS Virendra Singh, Adit D. Singh, Kewal K. Saluja
2015	—	`conf`	A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan. ATS Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh
2015	—	`conf`	A Soft Error Resilient Low Leakage SRAM Cell Design. ATS Adithyalal P. M, Shankar Balachandran, Virendra Singh
2015	C	`conf`	Application behavior aware re-reference interval prediction for shared LLC. ICCD Parth Lathigara, Shankar Balachandran, Virendra Singh
2015	—	`conf`	PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuits. VDAT Toral Shah, Anzhela Yu. Matrosova, Virendra Singh
2014	—	`conf`	A data-driven adaptive model-identification based large-scale sensor management system: Application to self powered neutron detectors. EAIS Nahit Pawar, Madhu N. Belur, Mani Bhushan, A. P. Tiwari, M. G. Kelkar, M. Pramanik, Virendra Singh
2014	J	`jnl`	Evaluation of Level of Confidence and Optimization of Roll-back Recovery with Checkpointing for Real-Time Systems. Microelectron. Reliab. Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson
2014	Misc	`conf`	Operand Isolation with Reduced Overhead for Low Power Datapath Design. VLSID Lokesh Siddhu, Amit Mishra, Virendra Singh
2014	—	`conf`	Partially programmable circuit design. EWDTS Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko, Virendra Singh
2014	—	`conf`	Temperature aware test scheduling by modified floorplanning. EWDTS Indira Rawat, M. K. Gupta, Virendra Singh
2013	—	`conf`	Delay testable sequential circuit designs. EWDTS Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Virendra Singh
2013	J	`jnl`	Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs. Autom. Remote. Control. Anzhela Yu. Matrosova, Sergey A. Ostanin, Virendra Singh
2013	—	`conf`	Level-Accurate Peak Activity Estimation in Combinational Circuit Using BILP. VDAT Jaynarayan T. Tudu, Deepak Malani, Virendra Singh
2013	—	`conf`	Observability calculation of state variable oriented to robust PDFs and LOC or LOS techniques. EWDTS Anzhela Yu. Matrosova, Sergey Ostanin, Alexey Melnikov, Virendra Singh
2013	—	`conf`	PDF testability of the circuits derived by special covering ROBDDs with gates. EWDTS Anzhela Yu. Matrosova, Ekaterina Nikolaeva, Dmitry Kudin, Virendra Singh
2013	—	`conf`	Scheduling tests for 3D SoCs with temperature constraints. EWDTS Indira Rawat, M. K. Gupta, Virendra Singh
2013	—	`conf`	Thermal analysis and modeling of 3D integrated circuits for test scheduling. 3DIC Indira Rawat, M. K. Gupta, Virendra Singh
2013	Misc	`conf`	Tutorial T10: Post - Silicon Validation, Debug and Diagnosis. VLSI Design Prabhat Mishra, Masahiro Fujita, Virendra Singh, Nagesh Tamarapalli, Sharad Kumar, Rajesh Mittal
2013	—	`ed.`	VLSI Design and Test, 17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, Revised Selected Papers VDAT Manoj Singh Gaur, Mark Zwolinski, Vijay Laxmi, Dharmendar Boolchandani, Virendra Singh, Adit D. Singh
2012	C	`ed.`	5th International Conference of Security of Information and Networks, SIN '12, Jaipur, India, October 22 - 26, 2012 SIN Manoj Singh Gaur, Atilla Elçi, Oleg B. Makarevich, Mehmet A. Orgun, Virendra Singh
2012	J	`jnl`	Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing. J. Electron. Test. Suraj Sindia, Vishwani D. Agrawal, Virendra Singh
2012	Misc	`conf`	Derating based hardware optimizations in soft error tolerant designs. VTS V. Prasanth, Virendra Singh, Rubin A. Parekhji
2012	C	`conf`	Efficient regular expression pattern matching for network intrusion detection systems using modified word-based automata. SIN Pawan Kumar, Virendra Singh
2012	—	`conf`	ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits. VDAT Jaynarayan T. Tudu, Deepak Malani, Virendra Singh
2012	C	`conf`	Impact of process variations on computers used for image processing. ISCAS Suraj Sindia, Fa Foster Dai, Vishwani D. Agrawal, Virendra Singh
2012	J	`jnl`	Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients. J. Electron. Test. Suraj Sindia, Vishwani D. Agrawal, Virendra Singh
2012	—	`conf`	SEU Tolerant Robust Latch Design. VDAT Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita
2012	C	`conf`	SEU tolerant robust memory cell design. IOLTS Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita
2011	C	`conf`	Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors. ICCD Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
2011	C	`conf`	C-Routing: An adaptive hierarchical NoC routing methodology. VLSI-SoC Manas Kumar Puthal, Virendra Singh, Manoj Singh Gaur, Vijay Laxmi
2011	—	`conf`	GA Based Congestion Aware Topology Generation for Application Specific NoC. DELTA Naveen Choudhary, Manoj Singh Gaur, Vijay Laxmi, Virendra Singh
2011	—	`conf`	Level of confidence evaluation and its usage for Roll-back Recovery with Checkpointing optimization. DSN Workshops Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson
2011	Misc	`conf`	Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients. VTS Suraj Sindia, Vishwani D. Agrawal, Virendra Singh
2011	C	`conf`	Parallelizing TUNAMI-N1 Using GPGPU. HPCC Harsh Gidra, Israrul Haque, Nitin P. Kumar, M. Sargurunathan, Manoj Singh Gaur, Vijay Laxmi, Mark Zwolinski, Virendra Singh
2011	C	`conf`	Reduced overhead soft error mitigation using error control coding techniques. IOLTS V. Prasanth, Virendra Singh, Rubin A. Parekhji
2011	—	`conf`	SEU tolerant SRAM cell. ISQED Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita
2011	—	`conf`	SSTKR: Secure and Testable Scan Design through Test Key Randomization. Asian Test Symposium Mohammed Abdul Razzaq, Virendra Singh, Adit D. Singh
2011	—	`conf`	Selection of the state variables for partial enhanced scan techniques. EWDTS Anzhela Yu. Matrosova, Alexey Melnikov, Ruslan Mukhamedov, Virendra Singh
2011	—	`conf`	Test and Diagnosis of Analog Circuits Using Moment Generating Functions. Asian Test Symposium Suraj Sindia, Vishwani D. Agrawal, Virendra Singh
2011	—	`conf`	Testing linear and non-linear analog circuits using moment generating functions. LATW Suraj Sindia, Vishwani D. Agrawal, Virendra Singh
2011	—	`conf`	Tutorial: "Post silicon debug of SOC designs". SoCC Virendra Singh, Masahiro Fujita
2010	A	`conf`	Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding. DSN Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
2010	—	`conf`	Energy-efficient redundant execution for chip multiprocessors. ACM Great Lakes Symposium on VLSI Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
2010	—	`conf`	Estimating Error-probability and its Application for Optimizing Roll-back Recovery with Checkpointing. DELTA Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson
2010	—	`conf`	FREP: A soft error resilient pipelined RISC architecture. EWDTS Viney Kumar, Rahul Raj Choudhary, Virendra Singh
2010	—	`conf`	Fault grading using Instruction-Execution graph. EWDTS K. R. Vinutha, Virendra Singh, Anzhela Yu. Matrosova, Manoj Singh Gaur
2010	C	`conf`	Genetic algorithm based topology generation for application specific Network-on-Chip. ISCAS Naveen Choudhary, Manoj Singh Gaur, Vijay Laxmi, Virendra Singh
2010	—	`conf`	Graph theoretic approach for scan cell reordering to minimize peak shift power. ACM Great Lakes Symposium on VLSI Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
2010	—	`conf`	Modified Scan Flip-Flop for Low Power Testing. Asian Test Symposium Amit Mishra, Nidhi Sinha, Satdev, Virendra Singh, Sreejit Chakravarty, Adit D. Singh
2010	B	`conf`	Modified T-Flip-Flop based scan cell for RAS. ETS Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Adit D. Singh
2010	A	`conf`	Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors. DATE Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
2010	Misc	`conf`	On Minimization of Test Application Time for RAS. VLSI Design Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh
2010	—	`conf`	On selection of state variables for delay test of identical functional units. EWDTS Aditi Kajala, Gayaprasad Sinsinwar, Rahul Raj Choudhary, Jaynarayan T. Tudu, Virendra Singh
2010	Misc	`conf`	Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients. VLSI Design Suraj Sindia, Virendra Singh, Vishwani D. Agrawal
2010	—	`conf`	Path delay faults and ENF. EWDTS Anzhela Yu. Matrosova, Valeriy B. Lipsky, Alexey Melnikov, Virendra Singh
2010	C	`conf`	Robust detection of soft errors using delayed capture methodology. IOLTS V. Prasanth, Virendra Singh, Rubin A. Parekhji
2010	—	`conf`	SEU tolerant SRAM for FPGA applications. FPT Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita
2010	B	`conf`	Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. ETS Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
2010	C	`conf`	Test application time minimization for RAS using basis optimization of column decoder. ISCAS A. Abhishek, Amanulla Khan, Virendra Singh, Kewal K. Saluja, Adit D. Singh
2010	—	`conf`	Thermal aware test scheduling for stacked multi-chip-modules. EWDTS N. S. Vinay, Indira Rawat, Erik Larsson, Manoj Singh Gaur, Virendra Singh
2009	—	`conf`	DX-compactor: distributed X-compaction for SoCs. ACM Great Lakes Symposium on VLSI Reshma C. Jumani, Niraj Bharatkumar Jain, Virendra Singh, Kewal K. Saluja
2009	A	`conf`	Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips. DATE Mikael Väyrynen, Virendra Singh, Erik Larsson
2009	—	`conf`	Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing. Asian Test Symposium K. G. Deepak, Robinson Reyna, Virendra Singh, Adit D. Singh
2009	—	`conf`	Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients. Asian Test Symposium Suraj Sindia, Virendra Singh, Vishwani D. Agrawal
2009	B	`conf`	On Minimization of Peak Power for Scan Circuit during Test. ETS Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Vishwani D. Agrawal
2009	—	`conf`	Polynomial coefficient based DC testing of non-linear analog circuits. ACM Great Lakes Symposium on VLSI Suraj Sindia, Virendra Singh, Vishwani D. Agrawal
2006	J	`jnl`	Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. IEEE Trans. Very Large Scale Integr. Syst. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
2005	J	`jnl`	Delay Fault Testing of Processor Cores in Functional Mode. IEICE Trans. Inf. Syst. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
2005	—	`conf`	Instruction-based delay fault self-testing of pipelined processor cores. ISCAS (6) Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
2005	B	`conf`	Testing Superscalar Processors in Functional Mode. FPL Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
2004	Misc	`conf`	Instruction-Based Delay Fault Self-Testing of Processor Cores. VLSI Design Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
2003	—	`conf`	Software-Based Delay Fault Testing of Processor Cores. Asian Test Symposium Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara