Vinícius Dal Bem

13 papers C 1Journal 5Unranked 6
YearRankTypeTitle / Venue / Authors
2017 J jnl
SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC.
IEEE Trans. Emerg. Top. Comput.
Vinícius Dal Bem, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
2016 — —
SAT based environment for logical capacity evaluation of via configurable block templates.
Vinícius Dal Bem
2013 — conf
Analytical logical effort formulation for minimum active area under delay constraints.
SBCCI
Caio G. P. Alegretti, Vinícius Dal Bem, Renato P. Ribas, André Inácio Reis
2013 J jnl
BTI and HCI first-order aging estimation for early use in standard cell technology mapping.
Microelectron. Reliab.
Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
2013 — conf
Logic synthesis for manufacturability considering regularity and lithography printability.
ISVLSI
Lucas Machado, Vinícius Dal Bem, Francesc Moll, Sergio Gómez, Renato P. Ribas, André Inácio Reis
2012 J jnl
Design of CMOS logic gates with enhanced robustness against aging degradation.
Microelectron. Reliab.
Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
2012 — conf
Lithography analysis of via-configurable transistor-array fabrics.
NORCHIP
Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
2011 — conf
Area impact analysis of via-configurable regular fabric for digital integrated circuit design.
SBCCI
Vinícius Dal Bem, Paulo F. Butzen, Carlos Eduardo Klock, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2011 C conf
Impact and optimization of lithography-aware regular layout in digital circuit design.
ICCD
Vinícius Dal Bem, Paulo F. Butzen, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
2011 — conf
Transistor Sizing Analysis of Regular Fabrics.
ARCS Workshops
Felipe S. Marranghello, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas, Francesc Moll
2011 — conf
Transistor sizing in lithography-aware regular fabrics.
SBCCI
Felipe S. Marranghello, Vinícius Dal Bem, André Inácio Reis, Francesc Moll, Renato P. Ribas
2010 J jnl
Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits.
J. Low Power Electron.
Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
2010 J jnl
Transistor network restructuring against NBTI degradation.
Microelectron. Reliab.
Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas