Vinod Kathail - RankMe

27 papers A* 3A 3Misc 4Journal 10Unranked 6

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Looking Back 25 Years to the HP Labs ASIC Synthesis Project, PICO. ASAP Robert Schreiber, Shail Aditya, Vinod Kathail
2024	J	`jnl`	AMD XDNA NPU in Ryzen AI Processors. IEEE Micro Alejandro Rico, Satyaprakash Pareek, Javier Cabezas, David Clarke, Baris Özgül, Francisco Barat, Yao Fu, Stephan Münz, Dylan Stuart, Patrick Schlangen, Pedro Duarte, Sneha Date, Indrani Paul, Jian Weng, Sonal Santan, Vinod Kathail, Ashish Sirasao, Juanjo Noguera
2024	J	`jnl`	Parallelization Strategies for DLRM Embedding Bag Operator on AMD CPUs. IEEE Micro Krishnakumar Nair, Avinash-Chandra Pandey, Siddappa Karabannavar, Meena Arunachalam, John Kalamatianos, Varun Agrawal, Saurabh Gupta, Ashish Sirasao, Elliott Delaye, Steven K. Reinhardt, Rajesh Vivekanandham, Ralph Wittig, Vinod Kathail, Padmini Gopalakrishnan, Satyaprakash Pareek, Rishabh Jain, Mahmut Taylan Kandemir, Jun-Liang Lin, Gulsum Gudukbay Akbulut, Chita R. Das
2020	A	`conf`	Xilinx Vitis Unified Software Platform. FPGA Vinod Kathail
2016	J	`jnl`	A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform. IEEE Micro Sagheer Ahmad, Vamsi Boppana, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig
2016	A	`conf`	SDSoC: A Higher-level Programming Environment for Zynq SoC and Ultrascale+ MPSoC. FPGA Vinod Kathail, James Hwang, Welson Sun, Yogesh Chobe, Tom Shui, Jorge Carrillo
2015	—	`conf`	UltraScale+ MPSoC and FPGA families. Hot Chips Symposium Vamsi Boppana, Sagheer Ahmad, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig
2010	Misc	`ed.`	Proceedings of the 2010 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2010, Scottsdale, AZ, USA, October 24-29, 2010 CASES Vinod Kathail, Reid Tatge, Rajeev Barua
2010	A	`conf`	Programming high performance signal processing systems in high level languages. FPGA Kees A. Vissers, Devada Varma, Vinod Kathail, Jeff Bier, Don MacMillen, Joseph R. Cavallaro
2008	Misc	`conf`	Architecture Exploration for Low Power Design. VLSI Design Vinod Kathail, Tom Miller
2007	Misc	`conf`	Tutorial T8A: Automated Application Engine Synthesis from C Algorithms. VLSI Design Vinod Kathail, Shail Aditya, Craig Gleason, Nagesh Chatekar
2002	J	`jnl`	PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators. J. VLSI Signal Process. Robert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman
2002	J	`jnl`	PICO: Automatically Designing Custom Computers. Computer Vinod Kathail, Shail Aditya, Robert Schreiber, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman
2001	J	`jnl`	Compiling for EPIC architectures. Proc. IEEE Vinod Kathail, Michael S. Schlansker, B. Ramakrishna Rau
2000	—	`conf`	High-Level Synthesis of Nonprogrammable Hardware Accelerators. ASAP Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider
1999	—	`conf`	Automatic Architectural Synthesis of VLIW and EPIC Processors. ISSS Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
1999	Misc	`conf`	Fine Grained Register Allocation for EPIC Processors With Predication. PDPTA Hansoo Kim, Vinod Kathail, Kanchi Gopinath, Bhagirath Narahari
1999	J	`jnl`	Machine-Description Driven Compilers for EPIC and VLIW Processors. Des. Autom. Embed. Syst. B. Ramakrishna Rau, Vinod Kathail, Shail Aditya
1999	—	`conf`	Register allocation in hyper-block for EPIC processors. PARCO Hansoo Kim, Kanchi Gopinath, Vinod Kathail
1998	J	`jnl`	Meld Scheduling: A Technique for Relaxing Scheduling Constraints. Int. J. Parallel Program. Santosh G. Abraham, Vinod Kathail, Brian L. Deitrich
1997	J	`jnl`	Techniques for critical path reduction of scalar programs. Int. J. Parallel Program. Michael S. Schlansker, Vinod Kathail
1996	A*	`conf`	Meld Scheduling: Relaxing Scheduling Constraints Across Region Boundaries. MICRO Santosh G. Abraham, Vinod Kathail, Brian L. Deitrich
1996	J	`jnl`	Parallelization of Control Recurrences for ILP Processors. Int. J. Parallel Program. Michael S. Schlansker, Vinod Kathail, Sadun Anik
1995	A*	`conf`	Critical path reduction for scalar programs. MICRO Michael S. Schlansker, Vinod Kathail
1994	A*	`conf`	Height reduction of control recurrences for ILP processors. MICRO Michael S. Schlansker, Vinod Kathail, Sadun Anik
1993	—	`conf`	Acceleration of First and Higher Order Recurrences on Processors with Instruction Level Parallelism. LCPC Michael S. Schlansker, Vinod Kathail
1990	—	`—`	Optimal interpreters for lambda-calculus based functional languages. Vinod Kathail