Vinod Ganesan

16 papers A 3Misc 1Journal 9Unranked 3
YearRankTypeTitle / Venue / Authors
2026 Misc conf
A 8-16 Gb/s/pin Full-Duplex Voltage-Mode Transmitter with Pulse Width Modulation Based Equalization and Analog Echo Canceller.
VLSID
Saurabh Saxena, Vinod Ganesan, Shubham Choudhary
2023 J jnl
A Survey of Security Concerns and Countermeasures in Modern Micro-architectures with Transient Execution.
CoRR
Nikhilesh Singh, Vinod Ganesan, Chester Rebeiro
2023 J jnl
PwR: Exploring the Role of Representations in Conversational Programming.
CoRR
Pradyumna YM, Vinod Ganesan, Dinesh Kumar Arumugam, Meghna Gupta, Nischith Shadagopan, Tanay Dixit, Sameer Segal, Pratyush Kumar, Mohit Jain, Sriram Rajamani
2022 J jnl
Design and Scaffolded Training of an Efficient DNN Operator for Computer Vision on the Edge.
ACM Trans. Embed. Comput. Syst.
Vinod Ganesan, Pratyush Kumar
2022 J jnl
Efficient ML Models for Practical Secure Inference.
CoRR
Vinod Ganesan, Anwesh Bhattacharya, Pratyush Kumar, Divya Gupta, Rahul Sharma, Nishanth Chandran
2021 J jnl
Design and Scaffolded Training of an Efficient DNN Operator for Computer Vision on the Edge.
CoRR
Vinod Ganesan, Pratyush Kumar
2021 A conf
FuSeConv: Fully Separable Convolutions for Fast Inference on Systolic Arrays.
DATE
Surya Selvam, Vinod Ganesan, Pratyush Kumar
2021 J jnl
FuSeConv: Fully Separable Convolutions for Fast Inference on Systolic Arrays.
CoRR
Surya Selvam, Vinod Ganesan, Pratyush Kumar
2021 — conf
Generalized Weight Agnostic Neural Networks for Configurable and Continual Autonomous Systems.
AIMLSystems
Pranav U. Gadikar, Vinod Ganesan, Pratyush Kumar Panda
2021 A conf
Seclusive Cache Hierarchy for Mitigating Cross-Core Cache and Coherence Directory Attacks.
DATE
Vishal Gupta, Vinod Ganesan, Biswabandan Panda
2021 J jnl
SuperShaper: Task-Agnostic Super Pre-training of BERT Models with Variable Hidden Dimensions.
CoRR
Vinod Ganesan, Gowtham Ramesh, Pratyush Kumar
2020 — conf
A Case for Generalizable DNN Cost Models for Mobile Devices.
IISWC
Vinod Ganesan, Surya Selvam, Sanchari Sen, Pratyush Kumar, Anand Raghunathan
2020 J jnl
Brutus: Refuting the Security Claims of the Cache Timing Randomization Countermeasure Proposed in CEASER.
IEEE Comput. Archit. Lett.
Rahul Bodduna, Vinod Ganesan, Patanjali SLPSK, Kamakoti Veezhinathan, Chester Rebeiro
2020 — conf
PARAM: A Microprocessor Hardened for Power Side-Channel Attack Resistance.
HOST
Muhammad Arsath K. F, Vinod Ganesan, Rahul Bodduna, Chester Rebeiro
2020 A conf
Sparsity-Aware Caches to Accelerate Deep Neural Networks.
DATE
Vinod Ganesan, Sanchari Sen, Pratyush Kumar, Neel Gala, Kamakoti Veezhinathan, Anand Raghunathan
2019 J jnl
PARAM: A Microprocessor Hardened for Power Side-Channel Attack Resistance.
CoRR
Muhammad Arsath K. F, Vinod Ganesan, Rahul Bodduna, Chester Rebeiro