Vinita Vasudevan

44 papers A* 5A 2C 1Misc 7Journal 27Unranked 2
YearRankTypeTitle / Venue / Authors
2024 J jnl
Exact Computation of Error in Approximate Circuits using SAT and Message-Passing Algorithms.
CoRR
S. Ramprasath, Marrivada Gopala Krishna Sai Charan, Vinita Vasudevan
2023 J jnl
A Framework for Reliability Analysis of Combinational Circuits Using Approximate Bayesian Inference.
IEEE Trans. Very Large Scale Integr. Syst.
Shivani Bathla, Vinita Vasudevan
2023 A* conf
Approximate inference of marginals using the IBIA framework.
NeurIPS
Shivani Bathla, Vinita Vasudevan
2023 J jnl
Approximate inference of marginals using the IBIA framework.
CoRR
Shivani Bathla, Vinita Vasudevan
2023 J jnl
IBIA: An Incremental Build-Infer-Approximate Framework for Approximate Inference of Partition Function.
CoRR
Shivani Bathla, Vinita Vasudevan
2023 J jnl
IBIA: An Incremental Build-Infer-Approximate Framework for Approximate Inference of Partition Function.
Trans. Mach. Learn. Res.
Shivani Bathla, Vinita Vasudevan
2022 J jnl
Fast and Accurate Proper Orthogonal Decomposition using Efficient Sampling and Iterative Techniques for Singular Value Decomposition.
ACM Trans. Math. Softw.
V. Charumathi, M. Ramakrishna, Vinita Vasudevan
2022 J jnl
IBIA: Bayesian Inference via Incremental Build-Infer-Approximate operations on Clique Trees.
CoRR
Shivani Bathla, Vinita Vasudevan
2022 J jnl
MPE inference using an Incremental Build-Infer-Approximate Paradigm.
CoRR
Shivani Bathla, Vinita Vasudevan
2021 J jnl
A Smoothed LASSO-Based DNN Sparsification Technique.
IEEE Trans. Circuits Syst. I Regul. Pap.
Basava Naga Girish Koneru, Nitin Chandrachoodan, Vinita Vasudevan
2021 J jnl
Analysis of power-accuracy trade-off in digital signal processing applications using low-power approximate adders.
IET Comput. Digit. Tech.
Celia Dharmaraj, Vinita Vasudevan, Nitin Chandrachoodan
2021 J jnl
Optimization of Signal Processing Applications Using Parameterized Error Models for Approximate Adders.
ACM Trans. Embed. Comput. Syst.
Celia Dharmaraj, Vinita Vasudevan, Nitin Chandrachoodan
2019 J jnl
Fast Proper Orthogonal Decomposition Using Improved Sampling and Iterative Techniques for Singular Value Decomposition.
CoRR
V. Charumathi, M. Ramakrishna, Vinita Vasudevan
2019 J jnl
Potential Critical Path Selection Based on a Time-Varying Statistical Timing Analysis Framework.
IEEE Trans. Very Large Scale Integr. Syst.
P. R. Chithira, Vinita Vasudevan
2019 J jnl
Sparse Artificial Neural Networks Using a Novel Smoothed LASSO Penalization.
IEEE Trans. Circuits Syst. II Express Briefs
Basava Naga Girish Koneru, Vinita Vasudevan
2018 A conf
Optimizing power-accuracy trade-off in approximate adders.
DATE
D. Celia, Vinita Vasudevan, Nitin Chandrachoodan
2018 C conf
Probabilistic Error Modeling for Two-part Segmented Approximate Adders.
ISCAS
D. Celia, Vinita Vasudevan, Nitin Chandrachoodan
2017 J jnl
A Hierarchical Singular Value Decomposition Algorithm for Low Rank Matrices.
CoRR
Vinita Vasudevan, M. Ramakrishna
2017 J jnl
A Hierarchical Technique for Statistical Path Selection and Criticality Computation.
ACM Trans. Design Autom. Electr. Syst.
P. R. Chithira, Vinita Vasudevan
2016 J jnl
A Skew-Normal Canonical Model for Statistical Static Timing Analysis.
IEEE Trans. Very Large Scale Integr. Syst.
Ramprasath S, Madiwalar Vijaykumar, Vinita Vasudevan
2016 J jnl
Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient.
ACM Trans. Design Autom. Electr. Syst.
Ramprasath S, Vinita Vasudevan
2015 A* conf
An efficient algorithm for frequency-weighted balanced truncation of VLSI interconnects in descriptor form.
DAC
Vinita Vasudevan, M. Ramakrishna
2015 A* conf
An efficient algorithm for statistical timing yield optimization.
DAC
S. Ramprasath, Vinita Vasudevan
2014 J jnl
Statistical Criticality Computation Using the Circuit Delay.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
S. Ramprasath, Vinita Vasudevan
2012 A conf
On the computation of criticality in statistical timing analysis.
ICCAD
S. Ramprasath, Vinita Vasudevan
2009 J jnl
Analysis of Clock Jitter in Continuous-Time Sigma-Delta Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Vinita Vasudevan
2006 J jnl
Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures.
IEEE Trans. Very Large Scale Integr. Syst.
K. N. Vikram, Vinita Vasudevan
2006 Misc conf
Scheduling divisible loads on partially reconfigurable hardware.
FCCM
K. N. Vikram, Vinita Vasudevan
2005 J jnl
A new technique for on-chip error estimation and reconfiguration of current-steering digital-to-analog converters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sunil Rafeeque, Vinita Vasudevan
2005 J jnl
Hardware-software co-simulation of bus-based reconfigurable systems.
Microprocess. Microsystems
K. N. Vikram, Vinita Vasudevan
2005 A* conf
Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits.
DAC
Vinita Vasudevan
2004 Misc conf
A Built-in-Self-Test Scheme for Digital to Analog Converters.
VLSI Design
Sunil Rafeeque, Vinita Vasudevan
2004 J jnl
A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs.
J. Electron. Test.
Sunil Rafeeque, Vinita Vasudevan
2004 J jnl
A simple technique to evaluate the noise spectral density in operational amplifier based circuits using the adjoint network theory.
IEEE Trans. Circuits Syst. I Regul. Pap.
Vinita Vasudevan
2004 J jnl
A time-domain technique for computation of noise-spectral density in linear and nonlinear time-varying circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Vinita Vasudevan
2004 — conf
An on-chip DNL estimation and reconfiguration for improved linearity in current steering DAC.
ISCAS (1)
Sunil Rafeeque, Vinita Vasudevan
2004 J jnl
Computation of the average and harmonic noise power-spectral density in switched-capacitor circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Vinita Vasudevan, M. Ramakrishna
2003 — conf
A time-domain technique for computation of noise spectral density in switched capacitor circuits.
ISCAS (1)
Vinita Vasudevan
2003 A* conf
Computation of noise spectral density in switched capacitor circuits using the mixed-frequency-time technique.
DAC
Vinita Vasudevan, M. Ramakrishna
2000 Misc conf
A Transistor Level Placement Tool for Custom Cell Generation.
VLSI Design
Ranjit K. Dash, T. Pramod, Vinita Vasudevan, M. Ramakrishna
2000 Misc conf
Optimization of the One-Dimensional Full Search Algorithm and Implementation Using an EPLD.
VLSI Design
Rajesh T. N. Rajaram, Vinita Vasudevan
1998 Misc conf
A Modified Line Expansion Algorithm for Device-level Routing of Analog Circuits.
VLSI Design
Prakash Gopalakrishnan, Vinita Vasudevan
1998 Misc conf
Symbolic Analysis of Analog Integrated Circuits.
VLSI Design
C. F. Prince, Vinita Vasudevan
1997 Misc conf
Synthesis of Analog CMOS Circuits.
VLSI Design
K. Ravi Shanker, Vinita Vasudevan