Vinicius N. Possani

15 papers A* 2A 2Journal 3Unranked 8
YearRankTypeTitle / Venue / Authors
2022 A conf
Majority-based Design Flow for AQFP Superconducting Family.
DATE
Giulia Meuli, Vinicius N. Possani, Rajinder Singh, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Patrick Vuillod, Luca G. Amarù, Scott Chase, Jamil Kawa, Giovanni De Micheli
2021 A* conf
LUT-Based Optimization For ASIC Design Flow.
DAC
Luca Gaetano Amarù, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli
2020 J jnl
Exact Benchmark Circuits for Logic Synthesis.
IEEE Des. Test
Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, Pierre-Emmanuel Gaillardon, André Inácio Reis, Renato Perez Ribas
2020 J jnl
Parallel Combinational Equivalence Checking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Vinicius N. Possani, Alan Mishchenko, Renato P. Ribas, André Inácio Reis
2020 A* conf
SAT-Sweeping Enhanced for Logic Synthesis.
DAC
Luca G. Amarù, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli
2018 — conf
Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation.
SBCCI
Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, André Inácio Reis, Renato P. Ribas
2018 A conf
Unlocking fine-grain parallelism for AIG rewriting.
ICCAD
Vinicius N. Possani, Yi-Shan Lu, Alan Mishchenko, Keshav Pingali, Renato P. Ribas, André Inácio Reis
2017 — conf
Binary adder circuit design using emerging MIGFET devices.
ISQED
Jeferson José Baqueta, Felipe S. Marranghello, Vinicius N. Possani, Augusto Neutzling, André Inácio Reis, Renato P. Ribas
2017 J jnl
Transistor Count Optimization in IG FinFET Network Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.
2016 — conf
Performance evaluation of optimized transistor networks built using independent-gate FinFET.
LASCAS
Andres M. A. Valdes, Vinicius N. Possani, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
2014 — conf
Exploring Independent Gates in FinFET-Based Transistor Network Generation.
SBCCI
Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar Soares da Rosa Júnior
2013 — conf
Efficient transistor-level design of CMOS gates.
ACM Great Lakes Symposium on VLSI
Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Júnior
2013 — conf
Improving the methodology to build non-series-parallel transistor arrangements.
SBCCI
Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.
2013 — conf
Transistor-level optimization of CMOS complex gates.
LASCAS
Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2012 — conf
NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements.
SBCCI
Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas