Vinicius Callegaro

18 papers C 3Journal 5Unranked 10
YearRankTypeTitle / Venue / Authors
2019 J jnl
Four-Level Forms for Memristive Material Implication Logic.
IEEE Trans. Very Large Scale Integr. Syst.
Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2018 J jnl
A Simple and Effective Heuristic Method for Threshold Logic Identification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Augusto Neutzling, Mayler G. A. Martins, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2016 J jnl
Graph-Based Transistor Network Generation Method for Supergate Design.
IEEE Trans. Very Large Scale Integr. Syst.
Vinicius Neves Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Júnior
2015 C conf
Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis.
ICCD
Vinicius Callegaro, Felipe S. Marranghello, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
2015 J jnl
Factored Forms for Memristive Material Implication Stateful Logic.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas
2015 C conf
Improved logic synthesis for memristive stateful logic using multi-memristor implication.
ISCAS
Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas
2015 C conf
SOP based logic synthesis for memristive IMPLY stateful logic.
ICCD
Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2013 — conf
Efficient transistor-level design of CMOS gates.
ACM Great Lakes Symposium on VLSI
Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Júnior
2013 — conf
Improving the methodology to build non-series-parallel transistor arrangements.
SBCCI
Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.
2013 — conf
Iterative remapping respecting timing constraints.
ISVLSI
Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis
2013 — conf
Read-polarity-once Boolean functions.
SBCCI
Vinicius Callegaro, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
2013 — conf
Transistor-level optimization of CMOS complex gates.
LASCAS
Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2012 — conf
KL-cut based digital circuit remapping.
NORCHIP
Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis
2012 — conf
NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements.
SBCCI
Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2011 — conf
Area impact analysis of via-configurable regular fabric for digital integrated circuit design.
SBCCI
Vinícius Dal Bem, Paulo F. Butzen, Carlos Eduardo Klock, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2011 J jnl
Contributions to the evaluation of ensembles of combinational logic gates.
Microelectron. J.
Renato P. Ribas, Simone Bavaresco, N. Schuch, Vinicius Callegaro, Marcelo Lubaszewski, André Inácio Reis
2011 — conf
Efficient method to compute minimum decision chains of Boolean functions.
ACM Great Lakes Symposium on VLSI
Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis
2010 — conf
SwitchCraft: a framework for transistor network design.
SBCCI
Vinicius Callegaro, Felipe de Souza Marques, Carlos Eduardo Klock, Leomar Soares da Rosa Júnior, Renato P. Ribas, André Inácio Reis