Vincent Huard

50 papers A 5C 5Misc 1Journal 14Unranked 25
YearRankTypeTitle / Venue / Authors
2025 conf
AICAS
Andrea Castagnetti, Alain Pegatoquet, Benoît Miramond, Olivier Montfort, Vincent Huard
2024 J jnl
IEICE Trans. Electron.
Ryuichi Nakajima, Takafumi Ito, Shotaro Sugitani, Tomoya Kii, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi, Mathieu Louvat, Francois Jacquet, Jean-Christophe Eloy, Olivier Montfort, Lionel Jure, Vincent Huard
2023 conf
ISSCC
Francesco Conti, Davide Rossi, Gianna Paulin, Angelo Garofalo, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Vincent Huard, Olivier Montfort, Lionel Jure, Nils Exibard, Pascal Gouedo, Mathieu Louvat, Emmanuel Botte, Luca Benini
2023 conf
ICICDT
Vincent Huard
2023 C conf
IOLTS
Shotaro Sugitani, Ryuichi Nakajima, Takafumi Ito, Jun Furuta, Kazutoshi Kobayashi, Mathieu Louvat, Francois Jacquet, Jean-Christophe Eloy, Olivier Montfort, Lionel Jure, Vincent Huard
2022 conf
RWS
Sidina Wane, T. V. Dinh, Q. H. Tran, Damienne Bajon, F. Ferrero, Lionel Duvillaret, Gwenaël Gaborit, Jacques Sombrin, E. de Lédinghen, P. Laban, Vincent Huard, Souhir Mhira, L. Tombakdjian, Philippe Ratajczak, A. Bousseksou
2022 conf
IRPS
Vincent Huard, Francois Jacquet, Souhir Mhira, Lionel Jure, Olivier Montfort, Mathieu Louvat, L. Zaia, F. Bertrand, E. Acacia, O. Caffin, H. Belhadj, O. Durand, Nils Exibard, Vincent Bonnet, A. Charvier, Paolo Bernardi, Riccardo Cantoro
2021 conf
ISSCC
Yasser Moursy, Thiago Raupp da Rosa, Lionel Jure, Anthony Quelen, Sébastien Genevey, Lionel Pierrefeu, Emmanuel G. Collins Jr., Joerg Winkler, Jonathan Park, Gaël Pillonnet, Vincent Huard, Andrea Bonzo, Philippe Flatresse
2021 conf
DFT
L. Degli Abbati, Rudolf Ullmann, G. Paganini, M. Coppetta, L. Zaia, Vincent Huard, Olivier Montfort, Riccardo Cantoro, Giorgio Insinga, F. Venini, P. Calao, Paolo Bernardi
2018 conf
IRPS
Xavier Garros, Alexandre Subirats, Gilles Reimbold, Fred Gaillard, Cheikh Diouf, X. Federspiel, Vincent Huard, M. Rafik
2018 conf
IRPS
Riddhi Jitendrakumar Shah, Florian Cacho, Vincent Huard, Souhir Mhira, D. Arora, Pankaj Agarwal, Shubham Kumar, S. Balaraman, Bijoy Kumar Singh, Lorena Anghel
2018 conf
IRPS
Vincent Huard, Cheikh Ndiaye, M. Arabi, Narendra Parihar, X. Federspiel, Souhir Mhira, S. Mahapatra, Alain Bravaix
2018 conf
IRPS
Vincent Huard, Souhir Mhira, A. Barclais, X. Lecocq, F. Raugi, M. Cantournet, Alain Bravaix
2018 conf
IRPS
M. Arabi, A. Cros, X. Federspiel, Cheikh Ndiaye, Vincent Huard, M. Rafik
2018 A conf
DATE
Ajith Sivadasan, Riddhi Jitendrakumar Shah, Vincent Huard, Florian Cacho, Lorena Anghel
2018 conf
IRPS
Souhir Mhira, Vincent Huard, D. Arora, Philippe Flatresse, Alain Bravaix
2017 J jnl
Microelectron. Reliab.
R. Lajmi, Florian Cacho, Estelle Lauga-Larroze, Sylvain Bourdel, Ph. Benech, Vincent Huard, X. Federspiel
2017 A conf
ITC
Souhir Mhira, Vincent Huard, Ahmed Benhassain, Florian Cacho, David Meyer, Sylvie Naudet, Abhishek Jain, C. R. Parthasarathy, Alain Bravaix
2017 C conf
IOLTS
Souhir Mhira, Vincent Huard, Ahmed Benhassain, Florian Cacho, Sylvie Naudet, Abhishek Jain, C. R. Parthasarathy, Alain Bravaix
2017 J jnl
Microelectron. Reliab.
Vincent Huard, Souhir Mhira, Florian Cacho, Alain Bravaix
2017 C conf
IOLTS
Florian Cacho, Ahmed Benhassain, Riddhi Jitendrakumar Shah, Souhir Mhira, Vincent Huard, Lorena Anghel
2017 A conf
DATE
Ajith Sivadasan, Armelle Notin, Vincent Huard, Etienne Maurin, Souhir Mhira, Florian Cacho, Lorena Anghel
2016 conf
VLSI Circuits
Rossella Ranica, Nicolas Planes, Vincent Huard, Olivier Weber, Daniel Noblet, Damien Croain, Fabien Giner, Sylvie Naudet, P. Mergault, S. Ibars, A. Villaret, Maryline Parra, Sébastien Haendler, M. Quoirin, Florian Cacho, C. Julien, F. Terrier, Lorenzo Ciampolini, David Turgis, Christophe Lecocq, Franck Arnaud
2016 C conf
IOLTS
Florian Cacho, Ahmed Benhassain, Souhir Mhira, Ajith Sivadasan, Vincent Huard, P. Cathelin, Vincent Knopik, Abhishek Jain, C. R. Parthasarathy, Lorena Anghel
2016 conf
ERMAVSS@DATE
Ahmed Benhassain, Florian Cacho, Vincent Huard, Lorena Anghel
2016 Misc conf
VTS
Lorena Anghel, Ahmed Benhassain, Ajith Sivadasan, Florian Cacho, Vincent Huard
2016 C conf
IOLTS
Alain Bravaix, M. Saliva, Florian Cacho, X. Federspiel, Cheikh Ndiaye, Souhir Mhira, Edith Kussener, E. Pauly, Vincent Huard
2016 conf
IVSW
Ahmed Benhassain, Souhir Mhira, Florian Cacho, Vincent Huard, Lorena Anghel
2016 J jnl
Microelectron. Reliab.
Cheikh Ndiaye, Vincent Huard, X. Federspiel, Florian Cacho, Alain Bravaix
2016 J jnl
Microelectron. Reliab.
Alain Bravaix, Florian Cacho, X. Federspiel, Cheikh Ndiaye, Souhir Mhira, Vincent Huard
2016 A conf
DATE
Ajith Sivadasan, Florian Cacho, Sidi Ahmed Benhassain, Vincent Huard, Lorena Anghel
2016 conf
ERMAVSS@DATE
Ajith Sivadasan, Florian Cacho, Sidi Ahmed Benhassain, Vincent Huard, Lorena Anghel
2015 conf
IRPS
P. Mora, X. Federspiel, Florian Cacho, Vincent Huard, Wafa Arfaoui
2015 A conf
DATE
M. Saliva, Florian Cacho, Vincent Huard, X. Federspiel, D. Angot, Ahmed Benhassain, Alain Bravaix, Lorena Anghel
2015 conf
IRPS
Vincent Huard, D. Angot, Florian Cacho
2015 conf
IRPS
M. Saliva, Florian Cacho, Cheikh Ndiaye, Vincent Huard, D. Angot, Alain Bravaix, Lorena Anghel
2015 conf
IRPS
A. Bezza, M. Rafik, David Roy, X. Federspiel, P. Mora, Cheikh Diouf, Vincent Huard, Gérard Ghibaudo
2015 conf
CICC
Ahmed Benhassain, Florian Cacho, Vincent Huard, M. Saliva, Lorena Anghel, C. R. Parthasarathy, Abhishek Jain, Fabien Giner
2015 conf
IRPS
Olivier Héron, Chiara Sandionigi, E. Piriou, Safa Mbarek, Vincent Huard
2012 J jnl
Microelectron. Reliab.
Yoann Mamy Randriamihaja, Vincent Huard, Xavier Federspiel, Alban Zaka, Pierpaolo Palestri, Denis Rideau, David Roy, Alain Bravaix
2011 J jnl
Microelectron. Reliab.
Vincent Huard, N. Ruiz Amador, Florian Cacho, E. Pion
2011 conf
CICC
N. Ruiz Amador, Vincent Huard, E. Pion, Florian Cacho, Damien Croain, V. Robert, Sylvain Engels, Philippe Flatresse, Lorena Anghel
2007 conf
PATMOS
C. R. Parthasarathy, Alain Bravaix, Chloe Guérin, Mickael Denais, Vincent Huard
2006 J jnl
Microelectron. Reliab.
C. R. Parthasarathy, Mickael Denais, Vincent Huard, G. Ribes, David Roy, Chloe Guérin, F. Perrier, E. Vincent, Alain Bravaix
2006 J jnl
Microelectron. Reliab.
Vincent Huard, Mickael Denais, C. R. Parthasarathy
2005 J jnl
Microelectron. Reliab.
Vincent Huard, Mickael Denais, F. Perrier, Nathalie Revil, C. R. Parthasarathy, Alain Bravaix, E. Vincent
2005 J jnl
Microelectron. Reliab.
Alain Bravaix, Didier Goguenheim, Mickael Denais, Vincent Huard, C. R. Parthasarathy, F. Perrier, Nathalie Revil, E. Vincent
2005 J jnl
Microelectron. Reliab.
G. Ribes, S. Bruyère, Mickael Denais, Frederic Monsieur, Vincent Huard, David Roy, Gérard Ghibaudo
2003 J jnl
Microelectron. Reliab.
G. Ribes, S. Bruyère, Frederic Monsieur, David Roy, Vincent Huard
2003 J jnl
Microelectron. Reliab.
Frederic Monsieur, E. Vincent, Vincent Huard, S. Bruyère, David Roy, Thomas Skotnicki, G. Pananakakis, Gérard Ghibaudo
redb/extractors/decompiler/bninja/analysis/cfg.py
← Index redb/extractors/decompiler/bninja/analysis/cfg.py python
from binaryninja.enums import LowLevelILOperation as LLIL_OP

# Support both package and standalone imports
try:
    from . import cfg_features
except ImportError:
    from redb.extractors.decompiler.bninja.analysis import cfg_features


# ---------------------------------------------------------------------------
# Task 2.2: Build LLIL operation maps at import time using real enum values
# ---------------------------------------------------------------------------

# Prime product map: LLIL operation integer value -> small prime
cfg_features.LLIL_OP_PRIMES = {
    # SET_REG, SET_REG_SPLIT
    LLIL_OP.LLIL_SET_REG.value: 2,
    LLIL_OP.LLIL_SET_REG_SPLIT.value: 2,
    # SET_FLAG
    LLIL_OP.LLIL_SET_FLAG.value: 3,
    # LOAD
    LLIL_OP.LLIL_LOAD.value: 5,
    # STORE
    LLIL_OP.LLIL_STORE.value: 7,
    # PUSH, POP
    LLIL_OP.LLIL_PUSH.value: 11,
    LLIL_OP.LLIL_POP.value: 13,
    # CALL, TAILCALL, SYSCALL
    LLIL_OP.LLIL_CALL.value: 17,
    LLIL_OP.LLIL_TAILCALL.value: 17,
    LLIL_OP.LLIL_SYSCALL.value: 19,
    # RET, NORET
    LLIL_OP.LLIL_RET.value: 23,
    LLIL_OP.LLIL_NORET.value: 23,
    # IF, GOTO
    LLIL_OP.LLIL_IF.value: 29,
    LLIL_OP.LLIL_GOTO.value: 31,
    # ADD, SUB
    LLIL_OP.LLIL_ADD.value: 37,
    LLIL_OP.LLIL_SUB.value: 41,
    # AND, OR, XOR
    LLIL_OP.LLIL_AND.value: 43,
    LLIL_OP.LLIL_OR.value: 47,
    LLIL_OP.LLIL_XOR.value: 53,
    # LSL, LSR, ASR, ROL, ROR
    LLIL_OP.LLIL_LSL.value: 59,
    LLIL_OP.LLIL_LSR.value: 61,
    LLIL_OP.LLIL_ASR.value: 67,
    LLIL_OP.LLIL_ROL.value: 71,
    LLIL_OP.LLIL_ROR.value: 73,
    # MUL, DIVU, DIVS, MODU, MODS
    LLIL_OP.LLIL_MUL.value: 79,
    LLIL_OP.LLIL_DIVU.value: 83,
    LLIL_OP.LLIL_DIVS.value: 83,
    LLIL_OP.LLIL_MODU.value: 89,
    LLIL_OP.LLIL_MODS.value: 89,
    # NEG, NOT
    LLIL_OP.LLIL_NEG.value: 97,
    LLIL_OP.LLIL_NOT.value: 101,
    # CMP_E, CMP_NE, CMP_SLT, CMP_ULT, CMP_SLE, CMP_ULE
    # CMP_SGT, CMP_UGT, CMP_SGE, CMP_UGE
    LLIL_OP.LLIL_CMP_E.value: 103,
    LLIL_OP.LLIL_CMP_NE.value: 103,
    LLIL_OP.LLIL_CMP_SLT.value: 107,
    LLIL_OP.LLIL_CMP_ULT.value: 107,
    LLIL_OP.LLIL_CMP_SLE.value: 109,
    LLIL_OP.LLIL_CMP_ULE.value: 109,
    LLIL_OP.LLIL_CMP_SGT.value: 113,
    LLIL_OP.LLIL_CMP_UGT.value: 113,
    LLIL_OP.LLIL_CMP_SGE.value: 127,
    LLIL_OP.LLIL_CMP_UGE.value: 127,
    # NOP
    LLIL_OP.LLIL_NOP.value: 1,
    # SX, ZX, LOW_PART, BOOL_TO_INT
    LLIL_OP.LLIL_SX.value: 131,
    LLIL_OP.LLIL_ZX.value: 137,
    LLIL_OP.LLIL_LOW_PART.value: 139,
    LLIL_OP.LLIL_BOOL_TO_INT.value: 149,
    # JUMP, JUMP_TO
    LLIL_OP.LLIL_JUMP.value: 151,
    LLIL_OP.LLIL_JUMP_TO.value: 151,
}

# Category map: LLIL operation integer value -> category index
_ARITHMETIC = {
    LLIL_OP.LLIL_ADD, LLIL_OP.LLIL_ADC, LLIL_OP.LLIL_SUB, LLIL_OP.LLIL_SBB,
    LLIL_OP.LLIL_MUL, LLIL_OP.LLIL_MULU_DP, LLIL_OP.LLIL_MULS_DP,
    LLIL_OP.LLIL_DIVU, LLIL_OP.LLIL_DIVU_DP, LLIL_OP.LLIL_DIVS,
    LLIL_OP.LLIL_DIVS_DP, LLIL_OP.LLIL_MODU, LLIL_OP.LLIL_MODS,
    LLIL_OP.LLIL_NEG,
}
_LOGIC = {
    LLIL_OP.LLIL_AND, LLIL_OP.LLIL_OR, LLIL_OP.LLIL_XOR, LLIL_OP.LLIL_NOT,
    LLIL_OP.LLIL_LSL, LLIL_OP.LLIL_LSR, LLIL_OP.LLIL_ASR,
    LLIL_OP.LLIL_ROL, LLIL_OP.LLIL_RLC, LLIL_OP.LLIL_ROR, LLIL_OP.LLIL_RRC,
}
_TRANSFER = {
    LLIL_OP.LLIL_SET_REG, LLIL_OP.LLIL_SET_REG_SPLIT, LLIL_OP.LLIL_SET_FLAG,
    LLIL_OP.LLIL_GOTO, LLIL_OP.LLIL_IF, LLIL_OP.LLIL_JUMP, LLIL_OP.LLIL_JUMP_TO,
    LLIL_OP.LLIL_RET, LLIL_OP.LLIL_NORET, LLIL_OP.LLIL_PUSH, LLIL_OP.LLIL_POP,
}
_CALL = {
    LLIL_OP.LLIL_CALL, LLIL_OP.LLIL_TAILCALL, LLIL_OP.LLIL_SYSCALL,
}
_COMPARISON = {
    LLIL_OP.LLIL_CMP_E, LLIL_OP.LLIL_CMP_NE,
    LLIL_OP.LLIL_CMP_SLT, LLIL_OP.LLIL_CMP_ULT,
    LLIL_OP.LLIL_CMP_SLE, LLIL_OP.LLIL_CMP_ULE,
    LLIL_OP.LLIL_CMP_SGE, LLIL_OP.LLIL_CMP_UGE,
    LLIL_OP.LLIL_CMP_SGT, LLIL_OP.LLIL_CMP_UGT,
    LLIL_OP.LLIL_TEST_BIT, LLIL_OP.LLIL_FLAG_COND,
}
_MEMORY = {
    LLIL_OP.LLIL_LOAD, LLIL_OP.LLIL_STORE,
}

cfg_features.LLIL_OP_CATEGORIES = {}
for _op in _ARITHMETIC:
    cfg_features.LLIL_OP_CATEGORIES[_op.value] = cfg_features.CAT_ARITHMETIC
for _op in _LOGIC:
    cfg_features.LLIL_OP_CATEGORIES[_op.value] = cfg_features.CAT_LOGIC
for _op in _TRANSFER:
    cfg_features.LLIL_OP_CATEGORIES[_op.value] = cfg_features.CAT_TRANSFER
for _op in _CALL:
    cfg_features.LLIL_OP_CATEGORIES[_op.value] = cfg_features.CAT_CALL
for _op in _COMPARISON:
    cfg_features.LLIL_OP_CATEGORIES[_op.value] = cfg_features.CAT_COMPARISON
for _op in _MEMORY:
    cfg_features.LLIL_OP_CATEGORIES[_op.value] = cfg_features.CAT_MEMORY

# Set of CALL operation values for counting
_CALL_OPS = {op.value for op in _CALL}


# ---------------------------------------------------------------------------
# Task 2.1 + 2.3: Rewritten CFGAnalysis
# ---------------------------------------------------------------------------

class CFGAnalysis:
    def __init__(self, function, llil_function=None):
        self.function = function
        self.llil_function = llil_function

    def extract_function_cfg(self):
        """Extract function-level CFG features as a flat dictionary."""

        if self.function is None:
            return None

        blocks = list(self.function.basic_blocks)
        if not blocks:
            return None

        n = len(blocks)

        # 1. Build index-based adjacency from Binary Ninja blocks
        addr_to_idx = {b.start: i for i, b in enumerate(blocks)}
        successors = [[] for _ in range(n)]
        predecessors = [[] for _ in range(n)]
        for i, block in enumerate(blocks):
            for edge in block.outgoing_edges:
                if edge.target is None:
                    continue
                target_idx = addr_to_idx.get(edge.target.start)
                if target_idx is not None:
                    successors[i].append(target_idx)
                    predecessors[target_idx].append(i)

        # 2. BFS order (reusable across multiple features)
        bfs = cfg_features.bfs_order(successors, n)

        # 3. Collect per-block LLIL operations (for prime product + ACFG features)
        block_llil_ops = self._collect_block_llil_ops(blocks, addr_to_idx, n)
        all_llil_ops = [op for block_ops in block_llil_ops for op in block_ops]

        # 4. Structural counts
        edge_count = sum(len(s) for s in successors)
        total_llil = sum(len(ops) for ops in block_llil_ops)
        call_count = sum(
            1 for ops in block_llil_ops for op in ops
            if op in _CALL_OPS
        )

        # 5. Compute all features
        bb_features = cfg_features.build_block_features(block_llil_ops, successors, n)

        return {
            "cfg_topology_hash": cfg_features.compute_topology_hash(successors, bfs, n),
            "block_count": n,
            "edge_count": edge_count,
            "llil_total_operations": total_llil,
            "call_count": call_count,
            "cyclomatic_complexity": edge_count - n + 2,
            "loop_count": cfg_features.count_back_edges(successors, n),
            "max_depth": cfg_features.bfs_max_depth(successors, n),
            "max_fan_out": max((len(s) for s in successors), default=0),
            "md_index_topdown": cfg_features.compute_md_index_topdown(successors, predecessors, bfs),
            "md_index_bottomup": cfg_features.compute_md_index_bottomup(successors, predecessors, n),
            "prime_product_llil": cfg_features.compute_prime_product(all_llil_ops),
            "cfg_feature_tlsh": cfg_features.compute_cfg_feature_tlsh(bb_features, bfs),
            "wl_minhash": cfg_features.compute_wl_minhash(successors, predecessors, bb_features, n),
            "bb_features": bb_features,
            "cfg_adjacency": cfg_features.pack_adjacency(successors),
        }

    def _collect_block_llil_ops(self, blocks, addr_to_idx, n):
        """
        Collect LLIL operation integers per native basic block.
        Walks the full expression tree of each instruction so that
        nested operations (e.g. ADD inside SET_REG) are captured.
        Returns list of n lists, one per block.
        """
        block_ops = [[] for _ in range(n)]

        if self.llil_function is None:
            return block_ops

        try:
            for llil_block in self.llil_function.basic_blocks:
                # Map LLIL block to native block via source_block
                if llil_block.source_block is not None:
                    native_idx = addr_to_idx.get(llil_block.source_block.start)
                    if native_idx is not None:
                        for instr in llil_block:
                            self._walk_llil_ops(instr, block_ops[native_idx])
        except Exception:
            pass  # Return empty ops — LLIL-dependent fields will be 0/null

        return block_ops

    @staticmethod
    def _walk_llil_ops(expr, ops_list):
        """Collect operation values from an LLIL expression tree iteratively."""
        stack = [expr]
        while stack:
            node = stack.pop()
            if hasattr(node, 'operation'):
                ops_list.append(node.operation.value)
            if hasattr(node, 'operands'):
                for operand in node.operands:
                    if hasattr(operand, 'operation'):
                        stack.append(operand)