Vinay Verma

16 papers A* 1A 3C 1Journal 8Unranked 3
YearRankTypeTitle / Venue / Authors
2024 J jnl
Block-level double JPEG compression detection for image forgery localization.
Multim. Tools Appl.
Vinay Verma, Deepak Singh, Nitin Khanna
2023 J jnl
A mathematical model for the novel coronavirus with effect of lockdown.
Int. J. Model. Simul. Sci. Comput.
Vinay Verma, Manju Agarwal, Ashish Verma
2022 — conf
Refinement Matters: Textual Description Needs to be Refined for Zero-shot Learning.
EMNLP (Findings)
Chandan Gautam, Sethupathy Parameswaran, Vinay Verma, Suresh Sundaram, Savitha Ramasamy
2021 J jnl
Q-matrix Unaware Double JPEG Detection using DCT-Domain Deep BiLSTM Network.
CoRR
Vinay Verma, Deepak Singh, Nitin Khanna
2021 J jnl
Speaker-independent source cell-phone identification for re-compressed and noisy audio recordings.
Multim. Tools Appl.
Vinay Verma, Nitin Khanna
2020 — conf
Double JPEG Compression Detection for Distinguishable Blocks in Images Compressed with Same Quantization Matrix.
MLSP
Abhinav Narayan Harish, Vinay Verma, Nitin Khanna
2019 — conf
CNN-based System for Speaker Independent Cell-Phone Identification from Recorded Audio.
CVPR Workshops
Vinay Verma, Nitin Khanna
2018 J jnl
DCT-domain deep convolutional neural networks for multiple JPEG compression classification.
Signal Process. Image Commun.
Vinay Verma, Nikita Agarwal, Nitin Khanna
2017 J jnl
DCT-domain Deep Convolutional Neural Networks for Multiple JPEG Compression Classification.
CoRR
Vinay Verma, Nikita Agarwal, Nitin Khanna
2013 C conf
An approach to complement electronics courses using virtual environment.
EDUCON
Jinu Jayachandran, Nina Joseph, Maheshwar Mangat, Vinay Verma, N. P. Narendra, Aniruddha Shastri, Devendra Patil, Madhumita Date, Joseph John, Mahesh B. Patil
2008 J jnl
Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shantanu Dutt, Vinay Verma, Vishal Suthar
2004 A* conf
Efficient on-line testing of FPGAs with provable diagnosabilities.
DAC
Vinay Verma, Shantanu Dutt, Vishal Suthar
2004 A conf
Roving testing using new built-in-self-tester designs for FPGAs.
FPGA
Vinay Verma, Shantanu Dutt
2002 J jnl
A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs.
ACM Trans. Design Autom. Electr. Syst.
Shantanu Dutt, Vinay Verma, Hasan Arslan
2001 A conf
A Search-Based Bump-and-Refit Approach to Incremental Routing for ECO Applications in FPGAs.
ICCAD
Vinay Verma, Shantanu Dutt
1999 A conf
Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications.
ITC
Miron Abramovici, Charles E. Stroud, Carter Hamilton, Sajitha Wijesuriya, Vinay Verma