Vinay Vashishtha

12 papers A 1C 2Journal 3Unranked 6
YearRankTypeTitle / Venue / Authors
2025 — conf
29.2 A 0.021µm
ISSCC
Xiaofei Wang, Yusung Kim, Gwanghyeon Baek, Kunal Girish Bannore, Kaushal Dave, Arash Joushaghani, Narae Kang, Minwoo Ko, Anandkumar Mahadevan Pillai, Hema Chandra Prakash Movva, Gyusung Park, Muktadir Rahman, Seenivasan Subramaniam, Vinay Vashishtha, Teng Yang, Zheng Guo, Eric A. Karl
2022 J jnl
ASAP5: A predictive PDK for the 5 nm node.
Microelectron. J.
Vinay Vashishtha, Lawrence T. Clark
2021 J jnl
Comparing bulk-Si FinFET and gate-all-around FETs for the 5 ​nm technology node.
Microelectron. J.
Vinay Vashishtha, Lawrence T. Clark
2017 A conf
ASAP7 predictive design kit development and cell design technology co-optimization: Invited paper.
ICCAD
Vinay Vashishtha, Manoj Vangala, Lawrence T. Clark
2017 — conf
Design flows and collateral for the ASAP7 7nm FinFET predictive process design kit.
MSE
Lawrence T. Clark, Vinay Vashishtha, David M. Harris, Samuel Dietrich, Zunyan Wang
2017 — conf
Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit.
ISQED
Vinay Vashishtha, Ankita Dosi, Lovish Masand, Lawrence T. Clark
2017 — conf
Design with sub-10 nm FinFET technologies.
CICC
Lawrence T. Clark, Vinay Vashishtha
2017 C conf
Robust 7-nm SRAM design on a predictive PDK.
ISCAS
Vinay Vashishtha, Manoj Vangala, Parv Sharma, Lawrence T. Clark
2016 J jnl
ASAP7: A 7-nm finFET predictive process design kit.
Microelectron. J.
Lawrence T. Clark, Vinay Vashishtha, Lucian Shifren, Aditya Gujja, Saurabh Sinha, Brian Cline, Chandarasekaran Ramamurthy, Greg Yeric
2015 — conf
A soft-error hardened process portable embedded microprocessor.
CICC
Vinay Vashishtha, Lawrence T. Clark, Srivatsan Chellappa, Anudeep R. Gogulamudi, Aditya Gujja, Chad Farnsworth
2015 — conf
Advanced encryption system with dynamic pipeline reconfiguration for minimum energy operation.
ISQED
Srivatsan Chellappa, Chandarasekaran Ramamurthy, Vinay Vashishtha, Lawrence T. Clark
2015 C conf
Delay and power tradeoffs for static and dynamic register files.
ISCAS
Vinay Vashishtha, Aditya Gujja, Lawrence T. Clark