Vinay Saripalli

15 papers A* 2A 2Misc 2Journal 4Unranked 5
YearRankTypeTitle / Venue / Authors
2024 A* conf
CDLS: Constraint Driven Generative AI Framework for Analog Layout Synthesis.
DAC
Prasanth Mangalagiri, Lynn Qian, Farrukh Zafar, Praveen Mosalikanti, Phoebe Chang, Arun Kurian, Vinay Saripalli
2013 J jnl
Design of energy-efficient circuits and systems using tunnel field effect transistors.
IET Circuits Devices Syst.
Ravindhiran Mukundrajan, Matthew Cotter, Sungmin Bae, Vinay Saripalli, Mary Jane Irwin, Suman Datta, Vijaykrishnan Narayanan
2013 J jnl
Steep-Slope Devices: From Dark to Dim Silicon.
IEEE Micro
Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta
2012 A conf
Design space exploration of workload-specific last-level caches.
ISLPED
Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir
2012 Misc conf
Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores.
CODES+ISSS
Emre Kultursay, Karthik Swaminathan, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta
2012 — conf
Ultra Low Power Circuit Design Using Tunnel FETs.
ISVLSI
Ravindhiran Mukundrajan, Matthew Cotter, Vinay Saripalli, Mary Jane Irwin, Suman Datta, Vijaykrishnan Narayanan
2011 A* conf
An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores.
DAC
Vinay Saripalli, Asit K. Mishra, Suman Datta, Vijaykrishnan Narayanan
2011 — conf
Enabling architectural innovations using non-volatile memory.
ACM Great Lakes Symposium on VLSI
Vijaykrishnan Narayanan, Vinay Saripalli, Karthik Swaminathan, Ravindhiran Mukundrajan, Guangyu Sun, Yuan Xie, Suman Datta
2011 J jnl
Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Vinay Saripalli, Guangyu Sun, Asit K. Mishra, Yuan Xie, Suman Datta, Vijaykrishnan Narayanan
2011 A conf
Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores.
ISLPED
Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta
2011 — conf
Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design.
NANOARCH
Vinay Saripalli, Suman Datta, Vijaykrishnan Narayanan, Jaydeep P. Kulkarni
2010 Misc conf
Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors.
VLSI Design
Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta
2010 J jnl
Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits.
J. Low Power Electron.
Vinay Saripalli, Lu Liu, Suman Datta, Vijaykrishnan Narayanan
2009 — conf
Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors.
NanoNet
Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta
2008 — conf
Reconfigurable BDD based quantum circuits.
NANOARCH
Soumya Eachempati, Vinay Saripalli, Narayanan Vijaykrishnan, Suman Datta