Vinay B. Y. Kumar

21 papers A 2C 1Misc 4Journal 6Unranked 8
YearRankTypeTitle / Venue / Authors
2025 — conf
On-the-fly Validation of Hierarchical Cache Coherence Protocols using Directed Testing.
ISVLSI
Abhinaba Chakraborty, Ansuman Banerjee, Vinay B. Y. Kumar, Arindam Mallik
2022 J jnl
AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Simei Yang, Debjyoti Bhattacharjee, Vinay B. Y. Kumar, Saikat Chatterjee, Sayandip De, Peter Debacker, Diederik Verkest, Arindam Mallik, Francky Catthoor
2021 A conf
Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks.
DATE
Anubhab Baksi, Shivam Bhasin, Jakub Breier, Anupam Chattopadhyay, Vinay B. Y. Kumar
2020 J jnl
A Novel Duplication Based Countermeasure To Statistical Ineffective Fault Analysis.
IACR Cryptol. ePrint Arch.
Anubhab Baksi, Vinay B. Y. Kumar, Banashri Karmakar, Shivam Bhasin, Dhiman Saha, Anupam Chattopadhyay
2020 Misc conf
A Novel Duplication Based Countermeasure to Statistical Ineffective Fault Analysis.
ACISP
Anubhab Baksi, Vinay B. Y. Kumar, Banashri Karmakar, Shivam Bhasin, Dhiman Saha, Anupam Chattopadhyay
2020 J jnl
Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks (Extended Version).
IACR Cryptol. ePrint Arch.
Anubhab Baksi, Shivam Bhasin, Jakub Breier, Anupam Chattopadhyay, Vinay B. Y. Kumar
2020 A conf
Post-Quantum Secure Boot.
DATE
Vinay B. Y. Kumar, Naina Gupta, Anupam Chattopadhyay, Michael Kasper, Christoph Krauß, Ruben Niederhagen
2020 — conf
Secure Your SoC: Building System-an-Chip Designs for Security.
SoCC
Shivam Bhasin, Trevor E. Carlson, Anupam Chattopadhyay, Vinay B. Y. Kumar, Avi Mendelson, Romain Poussier, Yaswanth Tavva
2020 J jnl
Towards Designing a Secure RISC-V System-on-Chip: ITUS.
J. Hardw. Syst. Secur.
Vinay B. Y. Kumar, Suman Deb, Naina Gupta, Shivam Bhasin, Jawad Haj-Yahya, Anupam Chattopadhyay, Avi Mendelson
2019 — conf
ITUS: A Secure RISC-V System-on-Chip.
SoCC
Vinay B. Y. Kumar, Anupam Chattopadhyay, Jawad Haj-Yahya, Avi Mendelson
2019 — conf
Recruiting Fault Tolerance Techniques for Microprocessor Security.
ATS
Vinay B. Y. Kumar, Suman Deb, Rupesh Kumar, Mustafa Khairallah, Anupam Chattopadhyay, Avi Mendelson
2018 Misc conf
Lightweight Forth Programmable NoCs.
VLSID
Vinay B. Y. Kumar, Deval Shah, Mandar Datar, Sachin B. Patkar
2016 Misc conf
Relaxation Based Circuit Simulation Acceleration over CPU-FPGA.
VLSID
Vinay B. Y. Kumar, Kulshreshth Dhiman, Mandar Datar, Akash Pacharne, H. Narayanan, Sachin B. Patkar
2015 J jnl
Framework for Application Mapping over Packet-Switched Network of FPGAs: Case Studies.
CoRR
Vinay B. Y. Kumar, Pinalkumar Engineer, Mandar Datar, Yatish Turakhia, Saurabh Agarwal, Sanket Diwale, Sachin B. Patkar
2015 — conf
Parallel two step random walk algorithm to analyze VLSI power grid networks.
VDAT
Satyabrata Dash, Vivek Bangera, Vinay B. Y. Kumar, Gaurav Trivedi, Sachin B. Patkar
2014 — conf
FPGA-based implementation of M4RM for matrix multiplication over GF(2).
VDAT
Vivek Kumar, Vinay B. Y. Kumar, Sachin B. Patkar
2014 — conf
Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems.
VLSI-DAT
Janak Porwal, Sanket Diwale, Vinay B. Y. Kumar, Sachin B. Patkar
2014 C conf
Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping.
ICCD
Vinay B. Y. Kumar, Shovan Maity, Sachin B. Patkar
2013 — conf
Hardware-software Scalable Architectures for Gaussian Elimination over GF(2) and Higher Galois Fields.
PECCS
Prateek Saxena, Vinay B. Y. Kumar, Dilawar Singh, H. Narayanan, Sachin B. Patkar
2010 J jnl
FPGA Based High Performance Double-Precision Matrix Multiplication.
Int. J. Parallel Program.
Vinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan
2009 Misc conf
FPGA Based High Performance Double-Precision Matrix Multiplication.
VLSI Design
Vinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan