Viktor Pus

28 papers A* 1A 4B 7C 6Misc 1Journal 2Unranked 6
YearRankTypeTitle / Venue / Authors
2020 C conf
Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs.
DSD
Lukás Kekely, Jakub Cabal, Viktor Pus, Jan Korenek
2018 A conf
Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput.
FPGA
Jakub Cabal, Pavel Benácek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek
2018 — conf
Demonstration of Full-Duplex Packet Transfers Over PCI Express with Sustained 200 Gbps Throughput.
FPT
Lukás Kekely, Martin Spinler, Stepán Friedl, Jiri Sikora, Jan Korenek, Viktor Pus
2018 J jnl
P4-To-VHDL: Automatic generation of high-speed input and output network blocks.
Microprocess. Microsystems
Pavel Benácek, Viktor Pus, Hana Kubátová, Tomás Cejka
2018 B conf
Verification of Generated RTL from P4 Source Code.
ICNP
Radek Isa, Pavel Benácek, Viktor Pus
2017 B conf
Line rate programmable packet processing in 100Gb networks.
FPL
Pavel Benácek, Viktor Pus, Jan Korenek, Michal Kekely
2016 B conf
Building a feedback loop to capture evidence of network incidents.
CNSM
Zdenek Rosa, Tomás Cejka, Martin Zádník, Viktor Pus
2016 — conf
High-speed regular expression matching with pipelined automata.
FPT
Denis Matousek, Jan Korenek, Viktor Pus
2016 Misc conf
P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers.
FCCM
Pavel Benácek, Viktor Pus, Hana Kubátová
2016 J jnl
Software Defined Monitoring of Application Protocols.
IEEE Trans. Computers
Lukas Kekely, Jan Kucera, Viktor Pus, Jan Korenek, Athanasios V. Vasilakos
2015 B conf
Hardware accelerated flow measurement of 100 Gb ethernet.
IM
Viktor Pus, Petr Velan, Lukas Kekely, Jan Korenek, Pavel Minarík
2015 B conf
High-density network flow monitoring.
IM
Petr Velan, Viktor Pus
2014 A conf
Application specific processor with high level synthesized instructions (abstract only).
FPGA
Viktor Pus, Pavel Benácek
2014 C conf
Architecture of Effective High-Speed Network Stream Merger.
DSD
Pavel Benácek, Hana Kubátová, Viktor Pus
2014 C conf
CRC based hashing in FPGA using DSP blocks.
DDECS
Tomás Závodník, Lukas Kekely, Viktor Pus
2014 C conf
Design methodology of configurable high performance packet parser for FPGA.
DDECS
Viktor Pus, Lukas Kekely, Jan Korenek
2014 A* conf
Software Defined Monitoring of application protocols.
INFOCOM
Lukas Kekely, Viktor Pus, Jan Korenek
2014 B conf
Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring.
FPL
Lukas Kekely, Viktor Pus, Pavel Benácek, Jan Korenek
2014 A conf
Using DSP blocks to compute CRC hash in FPGA (abstract only).
FPGA
Viktor Pus, Lukas Kekely, Tomás Závodník
2012 — —
Algoritmy klasifikace paketů ; Packet Classification Algorithms.
Viktor Pus
2012 — conf
Hardware Acceleration for Measurements in 100 Gb/s Networks.
AIMS
Viktor Pus
2012 — conf
Low-latency modular packet header parser for FPGA.
ANCS
Viktor Pus, Lukas Kekely, Jan Korenek
2012 B conf
Reducing memory in high-speed packet classification.
IWCMC
Viktor Pus, Jan Korenek
2011 C conf
Hardware architecture for packet classification with prefix coloring.
DDECS
Viktor Pus, Michal Kajan, Jan Korenek
2011 — conf
Netbench: Framework for Evaluation of Packet Processing Algorithms.
ANCS
Viktor Pus, Jiri Tobola, Vlastimil Kosar, Jan Kastil, Jan Korenek
2010 C conf
Memory optimizations for packet classification algorithms in FPGA.
DDECS
Viktor Pus, Juraj Blaho, Jan Korenek
2009 A conf
Fast and scalable packet classification using perfect hash functions.
FPGA
Viktor Pus, Jan Korenek
2009 — conf
Memory optimization for packet classification algorithms.
ANCS
Juraj Blaho, Jan Korenek, Viktor Pus