Vikramkumar Pudi

32 papers C 4Misc 2Journal 13Unranked 13

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Applying Differential Privacy for Real-Time Monitoring Systems via Compressive Sensing. IEEE Trans. Consumer Electron. Vikramkumar Pudi, Lakshmi Bhanuprakash Reddy Konduru, Balasubramanyam Appina, Anupam Chattopadhyay
2025	J	`jnl`	Design of Low-Complexity Quantized Compressive Sensing Using Measurement Predictive Coding. IEEE Trans. Very Large Scale Integr. Syst. Lakshmi Bhanuprakash Reddy Konduru, Vikramkumar Pudi, Balasubramanyam Appina
2025	J	`jnl`	In-Memory Implementation of an Approximate Adder With Reduced Latency and Error. IEEE Trans. Circuits Syst. I Regul. Pap. Vijaya Lakshmi, Vikramkumar Pudi, John Reuben
2024	—	`conf`	Design of Novel Systolic Array based NTT for CRYSTALS-Kyber scheme. APCCAS Keerthija Puli, Vikramkumar Pudi
2024	J	`jnl`	Image Compression Based on Near Lossless Predictive Measurement Coding for Block-Based Compressive Sensing. IEEE Trans. Circuits Syst. II Express Briefs K. Lakshmi BhanuPrakash Reddy, Vikramkumar Pudi, Balasubramanyam Appina, Anupam Chattopadhyay
2024	C	`conf`	Redefining Clock Network Construction: The Nested Flex Paradigm for Enhanced PPA Dynamics. ISCAS Lakshmi Sarvaani P, Subba Ramkumar Reddy Annapalli, Vikramkumar Pudi
2023	C	`conf`	A Configurable Multi Source Clock Tree Synthesis For High Frequency Network On Chips. ISCAS Lakshmi Sarvaani P, Subba Ramkumar Reddy Annapalli, Vikramkumar Pudi, Naga Teja Babu M
2023	Misc	`conf`	Design of Energy Efficient and Low Delay Posit Multiplier. VLSID K. Lakshmi BhanuPrakash Reddy, Haripriya R. S, Keerthija Puli, Subba Ramkumar Reddy Annapalli, Vikramkumar Pudi
2023	—	`conf`	Design of Low Power ALU for RISC-VISA. iSES Keerthija Puli, Vikramkumar Pudi
2023	—	`conf`	Harnessing Hybrid Clock Tree Topology to Boost PPA in Highly Utilized Designs. APCCAS Lakshmi Sarvaani P, Subba Ramkumar Reddy Annapalli, Vikramkumar Pudi
2022	J	`jnl`	A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic. IEEE Trans. Circuits Syst. I Regul. Pap. Vijaya Lakshmi, John Reuben, Vikramkumar Pudi
2022	J	`jnl`	Hardware Implementation of SpoC-128. IACR Cryptol. ePrint Arch. Ambati Sathvik, Tirunagari Rahul, Anubhab Baksi, Vikramkumar Pudi
2022	J	`jnl`	Inner Product Computation In-Memory Using Distributed Arithmetic. IEEE Trans. Circuits Syst. I Regul. Pap. Vijaya Lakshmi, Vikramkumar Pudi, John Reuben
2021	—	`conf`	Design of Energy-Efficient TSPC based D Flip-flop for CNTFET Technology. VDAT K. Lakshmi BhanuPrakash Reddy, K. B. Dheeraj Kumar, Vikramkumar Pudi
2021	—	`conf`	Design of Low Area and Low Power Systolic Serial Parallel Multiplier using CNTFETs. iSES K. B. Dheeraj Kumar, K. Lakshmi BhanuPrakash Reddy, Vikramkumar Pudi, Srinivasu Bodapati
2020	J	`jnl`	A Brain-Computer Interface Framework Based on Compressive Sensing and Deep Learning. IEEE Consumer Electron. Mag. Ritu Ranjan Shrivastwa, Vikramkumar Pudi, Duo Chen, Rosa Q. So, Anupam Chattopadhyay, Cuntai Guan
2020	—	`conf`	Cyber Security Protocol for Secure Traffic Monitoring Systems using PUF-based Key Management. iSES Vikramkumar Pudi, Srinivasu Bodapati, Sachin Kumar, Anupam Chattopadhyay
2019	—	`conf`	Lightweight Secure-Boot Architecture for RISC-V System-on-Chip. ISQED Jawad Haj-Yahya, Ming Ming Wong, Vikramkumar Pudi, Shivam Bhasin, Anupam Chattopadhyay
2019	J	`jnl`	New Majority Gate-Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata. IEEE Trans. Circuits Syst. II Express Briefs Tingting Zhang, Vikramkumar Pudi, Weiqiang Liu
2018	—	`conf`	An FPGA-Based Brain Computer Interfacing Using Compressive Sensing and Machine Learning. ISVLSI Ritu Ranjan Shrivastwa, Vikramkumar Pudi, Anupam Chattopadhyay
2018	—	`conf`	CoLPUF : A Novel Configurable LFSR-based PUF. APCCAS B. Srinivasu, Vikramkumar Pudi, Anupam Chattopadhyay, Kwok-Yan Lam
2018	C	`conf`	Efficient and Lightweight Quantized Compressive Sensing using μ-Law. ISCAS Vikramkumar Pudi, Anupam Chattopadhyay, Kwok-Yan Lam
2018	—	`conf`	Lightweight ASIC Implementation of AEGIS-128. ISVLSI Anubhab Baksi, Vikramkumar Pudi, Swagata Mandal, Anupam Chattopadhyay
2018	C	`conf`	Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor. VLSI-SoC Ming Ming Wong, Vikramkumar Pudi, Anupam Chattopadhyay
2018	J	`jnl`	Secure and Lightweight Compressive Sensing Using Stream Cipher. IEEE Trans. Circuits Syst. II Express Briefs Vikramkumar Pudi, Anupam Chattopadhyay, Kwok-Yan Lam
2018	Misc	`conf`	Security Vulnerabilities of Unmanned Aerial Vehicles and Countermeasures: An Experimental Study. VLSID Vishal Dey, Vikramkumar Pudi, Anupam Chattopadhyay, Yuval Elovici
2017	J	`jnl`	Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity. IEEE Trans. Computers Vikramkumar Pudi, K. Sridharan, Fabrizio Lombardi
2017	—	`conf`	SHA-3 implementation using ReRAM based in-memory computing architecture. ISQED Debjyoti Bhattacharjee, Vikramkumar Pudi, Anupam Chattopadhyay
2016	—	`conf`	FPGA Based Cyber Security Protocol for Automated Traffic Monitoring Systems: Proposal and Implementation. ISVLSI Anupam Chattopadhyay, Vikramkumar Pudi, Anubhab Baksi, Thambipillai Srikanthan
2016	—	`conf`	Modified projected Landweber method for Compressive-Sensing reconstruction of images with non-orthogonal matrices. ISIC Vikramkumar Pudi, Anupam Chattopadhyay, Thambipillai Srikanthan
2015	J	`jnl`	A Bit-Serial Pipelined Architecture for High-Performance DHT Computation in Quantum-Dot Cellular Automata. IEEE Trans. Very Large Scale Integr. Syst. Vikramkumar Pudi, K. Sridharan
2015	J	`jnl`	Very large-scale integration architecture for video stabilisation and implementation on a field programmable gate array-based autonomous vehicle. IET Comput. Vis. Tahiyah Nou Shene, Vikramkumar Pudi, K. Sridharan, Vineetha Thomas, J. Arthi