Vikram Jain - RankMe

23 papers A* 2A 2C 1Journal 13Unranked 5

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	MAVERIC: A Heterogeneous Robotics SoC With 4 CPU Cores and 13 INT8/FP32 Accelerators in 16-nm-Class Technology. IEEE J. Solid State Circuits Seah Kim, Jerry Zhao, Roger Hsiao, Yufeng Chi, Vighnesh Iyer, Vikram Jain, Borivoje Nikolic, Yakun Sophia Shao
2025	J	`jnl`	BitWave: Exploiting Column-Based Bit-Level Sparsity for Deep Learning Acceleration. CoRR Man Shi, Vikram Jain, Antony Joseph, Maurice Meijer, Marian Verhelst
2025	—	`conf`	Characterizing and Optimizing Real-Time Optimal Control for Embedded SoCs. IISWC Shengjun Kris Dong, Dima Nikiforov, Widyadewi Soedarmadji, Minh Nguyen, Vikram Jain, Christopher W. Fletcher, Yakun Sophia Shao
2025	J	`jnl`	Enabling Efficient Hardware Acceleration of Hybrid Vision Transformer (ViT) Networks at the Edge. CoRR Joren Dumoulin, Pouya Houshmand, Vikram Jain, Marian Verhelst
2024	A*	`conf`	BitWave: Exploiting Column-Based Bit-Level Sparsity for Deep Learning Acceleration. HPCA Man Shi, Vikram Jain, Antony Joseph, Maurice Meijer, Marian Verhelst
2024	A	`conf`	Design Approach for Die-to-Die Interfaces to Enable Energy-Efficient Chiplet Systems. ISLPED Vikram Jain, Wei Tang, Zuoguo Wu, Viansa Schmulbach, Yakun Sophia Shao, Zhengya Zhang, Borivoje Nikolic
2024	C	`conf`	Enabling Efficient Hardware Acceleration of Hybrid Vision Transformer (ViT) Networks at the Edge. ISCAS Joren Dumoulin, Pouya Houshmand, Vikram Jain, Marian Verhelst
2023	J	`jnl`	DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge. IEEE J. Solid State Circuits Pouya Houshmand, Giuseppe Maria Sarda, Vikram Jain, Kodai Ueyoshi, Ioannis A. Papistas, Man Shi, Qilin Zheng, Debjyoti Bhattacharjee, Arindam Mallik, Peter Debacker, Diederik Verkest, Marian Verhelst
2023	A*	`conf`	PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge. DAC Vikram Jain, Matheus A. Cavalcante, Nazareno Bruschi, Michael Rogenmoser, Thomas Benz, Andreas Kurth, Davide Rossi, Luca Benini, Marian Verhelst
2023	J	`jnl`	PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge. CoRR Vikram Jain, Matheus A. Cavalcante, Nazareno Bruschi, Michael Rogenmoser, Thomas Benz, Andreas Kurth, Davide Rossi, Luca Benini, Marian Verhelst
2023	A	`conf`	PetaOps/W edge-AI $\mu$ Processors: Myth or reality? DATE Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Friedemann Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, Sam Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal
2023	J	`jnl`	TinyVers: A Tiny Versatile System-on-Chip With State-Retentive eMRAM for ML Inference at the Extreme Edge. IEEE J. Solid State Circuits Vikram Jain, Juan Sebastian Piedrahita Giraldo, Jaro De Roose, Linyan Mei, Bert Boons, Marian Verhelst
2023	J	`jnl`	TinyVers: A Tiny Versatile System-on-chip with State-Retentive eMRAM for ML Inference at the Extreme Edge. CoRR Vikram Jain, Juan Sebastian Piedrahita Giraldo, Jaro De Roose, Linyan Mei, Bert Boons, Marian Verhelst
2022	J	`jnl`	CONVOLVE: Smart and seamless design of smart edge processors. CoRR Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Frank K. Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, S. Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal
2022	—	`conf`	DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC. ISSCC Kodai Ueyoshi, Ioannis A. Papistas, Pouya Houshmand, Giuseppe Maria Sarda, Vikram Jain, Man Shi, Qilin Zheng, Juan Sebastian Piedrahita Giraldo, Peter Vrancx, Jonas Doevenspeck, Debjyoti Bhattacharjee, Stefan Cosemans, Arindam Mallik, Peter Debacker, Diederik Verkest, Marian Verhelst
2022	J	`jnl`	Enabling real-time object detection on low cost FPGAs. J. Real Time Image Process. Vikram Jain, Ninad Jadhav, Marian Verhelst
2022	—	`conf`	TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge. VLSI Technology and Circuits Vikram Jain, Juan Sebastian Piedrahita Giraldo, Jaro De Roose, Bert Boons, Linyan Mei, Marian Verhelst
2021	—	`conf`	Analyzing the Energy-Latency-Area-Accuracy Trade-off Across Contemporary Neural Networks. AICAS Vikram Jain, Linyan Mei, Marian Verhelst
2021	J	`jnl`	Efficient Execution of Temporal Convolutional Networks for Embedded Keyword Spotting. IEEE Trans. Very Large Scale Integr. Syst. Juan Sebastian Piedrahita Giraldo, Vikram Jain, Marian Verhelst
2021	J	`jnl`	Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder. IEEE Trans. Circuits Syst. I Regul. Pap. Vikram Jain, Christoffer Fougstedt, Per Larsson-Edefors
2021	J	`jnl`	ZigZag: Enlarging Joint Architecture-Mapping Design Space Exploration for DNN Accelerators. IEEE Trans. Computers Linyan Mei, Pouya Houshmand, Vikram Jain, Juan Sebastian Piedrahita Giraldo, Marian Verhelst
2020	J	`jnl`	ZigZag: A Memory-Centric Rapid DNN Accelerator Design Space Exploration Framework. CoRR Linyan Mei, Pouya Houshmand, Vikram Jain, Juan Sebastian Piedrahita Giraldo, Marian Verhelst
2019	—	`conf`	Variable-Rate FEC Decoder VLSI Architecture for 400G Rate-Adaptive Optical Communication. ICECS Vikram Jain, Christoffer Fougstedt, Per Larsson-Edefors