Vikram Iyengar

47 papers A* 3A 12Misc 9Journal 14Unranked 7
YearRankTypeTitle / Venue / Authors
2012 J jnl
Physically-Aware N-Detect Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yen-Tzu Lin, Osei Poku, R. D. (Shawn) Blanton, Phil Nigh, Peter Lloyd, Vikram Iyengar
2010 A conf
Low cost at-speed testing using On-Product Clock Generation compatible with test compression.
ITC
Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise
2009 J jnl
Wafer-Level Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs.
IEEE Trans. Very Large Scale Integr. Syst.
Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar
2008 A conf
Evaluating the Effectiveness of Physically-Aware N-Detect Test using Real Silicon.
ITC
Yen-Tzu Lin, Osei Poku, Ronald D. Blanton, Phil Nigh, Peter Lloyd, Vikram Iyengar
2007 — conf
AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs.
ASP-DAC
Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar
2007 Misc conf
An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs.
VTS
Vikram Iyengar, Kenneth Pichamuthu, Andrew Ferko, Frank Woytowich, David E. Lackey, Gary Grise, Mark Taylor, Mike Degregorio, Steven F. Oakland
2007 A conf
Variation-aware performance verification using at-speed structural test and statistical timing.
ICCAD
Vikram Iyengar, Jinjun Xiong, Subbayyan Venkatesan, Vladimir Zolotov, David E. Lackey, Peter A. Habitz, Chandu Visweswariah
2006 A* conf
A flexible and scalable methodology for GHz-speed structural test.
DAC
Vikram Iyengar, Gary Grise, Mark Taylor
2006 A conf
At-Speed Structural Test For High-Performance ASICs.
ITC
Vikram Iyengar, Toshihiko Yokota, Kazuhiro Yamada, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Mark Johnson, Dave Milton, Mark Taylor, Frank Woytowich
2006 — conf
Design For At-Speed Structural Test And Performance Verification Of High-Performance ASICs.
CICC
Vikram Iyengar, Mark Johnson, Theo Anemikos, Gary Grise, Mark Taylor, Raymond Farmer, Frank Woytowich, Bob Bassett
2006 — conf
Performance verification of high-performance ASICs using at-speed structural test.
ACM Great Lakes Symposium on VLSI
Vikram Iyengar, Mark Johnson, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Phil Stevens, Mark Taylor, Frank Woytowich
2006 A conf
Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking.
DATE
Chunsheng Liu, Vikram Iyengar
2006 Misc conf
Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking.
VTS
Chunsheng Liu, Vikram Iyengar, Dhiraj K. Pradhan
2005 — conf
Defect-Oriented Test for Ultra-Low DPM.
Asian Test Symposium
Vikram Iyengar, Phil Nigh
2005 Misc conf
Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking.
VTS
Chunsheng Liu, Vikram Iyengar, Jiangfan Shi, Érika F. Cota
2005 J jnl
Test planning for modular testing of hierarchical SOCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Krishnendu Chakrabarty, Vikram Iyengar, Mark D. Krasniewski
2005 — conf
Thermal-Aware Test Scheduling and Hot Spot Temperature Minimization for Core-Based Systems.
DFT
Chunsheng Liu, Kugesh Veeraraghavant, Vikram Iyengar
2005 A conf
User interfaces for continuum robot arms.
IROS
Matthew A. Csencsits, Bryan A. Jones, William McMahan, Vikram Iyengar, Ian D. Walker
2004 J jnl
SOC test planning using virtual test access architectures.
IEEE Trans. Very Large Scale Integr. Syst.
Anuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty
2003 — conf
A Uni.ed SOC Test Approach Based on Test Data Compression and TAM Design.
DFT
Vikram Iyengar, Anshuman Chandra
2003 A conf
A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization.
DATE
Vikram Iyengar, Anshuman Chandra, Sharon Schweizer, Krishnendu Chakrabarty
2003 Misc conf
Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs.
VTS
Vikram Iyengar, Krishnendu Chakrabarty, Mark D. Krasniewski, Gopind N. Kumar
2003 J jnl
Efficient test access mechanism optimization for system-on-chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
2003 J jnl
Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip.
IEEE Trans. Computers
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
2003 A* conf
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers.
DAC
Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski, Krishnendu Chakrabarty
2002 A conf
A Set of Benchmarks fo Modular Testing of SOCs.
ITC
Erik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty
2002 A conf
Efficient Wrapper/TAM Co-Optimization for Large SOCs.
DATE
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
2002 Misc conf
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization.
VTS
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
2002 A conf
On the Use of k-tuples for SoC Test Schedule Representation.
ITC
Sandeep Koranne, Vikram Iyengar
2002 — conf
Recent Advances in Test Planning for Modular Testing of Core-Based SOCs.
Asian Test Symposium
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
2002 J jnl
System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Vikram Iyengar, Krishnendu Chakrabarty
2002 J jnl
Test Bus Sizing for System-on-a-Chip.
IEEE Trans. Computers
Vikram Iyengar, Krishnendu Chakrabarty
2002 A conf
Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints.
ITC
Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
2002 — book
Test Resource Partitioning for System-on-a-Chip.
Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
2002 J jnl
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip.
J. Electron. Test.
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
2002 A* conf
Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs.
DAC
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
2001 Misc conf
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip.
VTS
Vikram Iyengar, Krishnendu Chakrabarty
2001 A conf
Test wrapper and test access mechanism co-optimization for system-on-chip.
ITC
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
2000 J jnl
A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors.
J. Electron. Test.
Ta-Chung Chang, Vikram Iyengar, Elizabeth M. Rudnick
2000 J jnl
Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters.
IEEE Trans. Very Large Scale Integr. Syst.
Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar
2000 Misc conf
Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores.
PDPTA
Hiroshi Date, Vikram Iyengar, Krishnendu Chakrabarty, Makoto Sugihara
1999 Misc conf
Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters.
VTS
Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar
1999 J jnl
Deterministic Built-in Pattern Generation for Sequential Circuits.
J. Electron. Test.
Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray
1999 — ch.
Microprocessor Design Verification.
The VLSI Handbook
Vikram Iyengar, Elizabeth M. Rudnick
1998 Misc conf
Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets.
VTS
Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray
1998 J jnl
Huffman encoding of test sets for sequential circuits.
IEEE Trans. Instrum. Meas.
Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray
1997 J jnl
An Efficient Finite-State Machine Implementation of Huffman Decoders.
Inf. Process. Lett.
Vikram Iyengar, Krishnendu Chakrabarty