Vijaya Sankara Rao Pasupureddi

40 papers C 8Misc 5Journal 13Unranked 14
YearRankTypeTitle / Venue / Authors
2023 J jnl
An adaptive link training based hybrid circuit topology for full-duplex on-chip interconnects.
Int. J. Circuit Theory Appl.
Prema Kumar Govindaswamy, Raviteja Kammari, Vijaya Sankara Rao Pasupureddi
2022 C conf
A Low-Power Half-Rate Charge-Steering Hybrid for Full-Duplex Chip-to-Chip Interconnects.
ISCAS
Prema Kumar Govindaswamy, Nijwm Wary, Vijaya Sankara Rao Pasupureddi
2022 J jnl
A power-efficient current-integrating hybrid for full-duplex communication over chip-to-chip interconnects.
Int. J. Circuit Theory Appl.
Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi
2022 — conf
Digitally Intensive Sub-sampling Mixer-First Direct Down-Conversion Receiver Architecture.
MWSCAS
Rakesh Rena, Raviteja Kammari, Vijaya Sankara Rao Pasupureddi
2022 C conf
Power Efficient Echo-Cancellation Based Hybrid for Full-Duplex Chip-to-Chip Interconnects.
ISCAS
Prema Kumar Govindaswamy, Nijwm Wary, Vijaya Sankara Rao Pasupureddi
2021 J jnl
A 2
Circuits Syst. Signal Process.
Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi
2021 C conf
A Process Scalable Architecture for Low Noise Figure Sub-Sampling Mixer-First RF Front-End.
ISCAS
Rakesh Rena, Suraj Kumar Verma, Vijaya Sankara Rao Pasupureddi
2020 — conf
A 2^7 -1 Low-Power Half-Rate 16-Gb/s Charge-Mode PRBS Generator in 1.2V, 65nm CMOS.
ISVLSI
Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi
2020 C conf
An Adaptive Hybrid with Residue Monitor for Full-Duplex On-Chip Interconnects.
ISCAS
Pankaj Venuturupalli, Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi
2020 J jnl
Charge controlled delay element enabled widely linear power efficient MPCG-MDLL in 1.2V, 65nm CMOS.
Int. J. Circuit Theory Appl.
Raviteja Kammari, Vijaya Sankara Rao Pasupureddi
2020 J jnl
Residue monitor enabled charge-mode adaptive echo-cancellation for simultaneous bidirectional signaling over on-chip interconnects.
Microelectron. J.
Pankaj Venuturupalli, Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi
2019 J jnl
A -40 dB EVM, 77 MHz Dual-Band Tunable Gain Sub-Sampling Receiver Front End in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ajinkya Kale, Suchendranath Popuri, Michael Koeberle, Johannes Sturm, Vijaya Sankara Rao Pasupureddi
2019 J jnl
A -40-dB EVM 20-MHz subsampling multistandard receiver architecture with dynamic carrier detection, bandwidth estimation, and EVM optimization.
Int. J. Circuit Theory Appl.
Ajinkya Kale, Johannes Sturm, Vijaya Sankara Rao Pasupureddi
2019 — conf
A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS.
VDAT
Raviteja Kammari, Vijaya Sankara Rao Pasupureddi
2018 — conf
0.9 to 2.5 GHz Sub-Sampling Receiver Architecture for Dynamically Reconfigurable SDR.
ISVLSI
Ajinkya Kale, Johannes Sturm, Vijaya Sankara Rao Pasupureddi
2018 J jnl
Integration solutions for reconfigurable multi-standard wireless transceivers.
Elektrotech. Informationstechnik
Ajinkya Kale, Graciele Batistell, Suchendranath Popuri, Vijaya Sankara Rao Pasupureddi, Wolfgang Bösch, Johannes Sturm
2016 J jnl
100-Mb/s enhanced data rate MIL-STD-1553B controller in 65-nm CMOS technology.
IEEE Trans. Aerosp. Electron. Syst.
Prateek Pendyala, Vijaya Sankara Rao Pasupureddi
2016 C conf
A low power charge mode compressive acquisition of multichannel EEG signals.
ISCAS
Bhuvanan Kaliannan, Vijaya Sankara Rao Pasupureddi
2016 C conf
A new hybrid circuit topology for simultaneous bidirectional signaling over on-chip interconnects.
ISCAS
Divya Duvvuri, Somanshu Agarwal, Vijaya Sankara Rao Pasupureddi
2016 — conf
A tunable gain and tunable band active balun LNA for IEEE 802.11ac WLAN receivers.
ESSCIRC
Suchendranath Popuri, Vijaya Sankara Rao Pasupureddi, Johannes Sturm
2016 — conf
An Integrated Common Gate CTLE Receiver Front End with Charge Mode Adaptation.
ISVLSI
Divya Duvvuri, Vijaya Sankara Rao Pasupureddi
2016 — conf
Backward compatible MIL-STD-1553B analog transceiver upgrade for 100-Mb/s data rate.
VDAT
Prateek Pendyala, Vijaya Sankara Rao Pasupureddi
2016 J jnl
Design and analysis of a current mode integrated CTLE with charge mode adaptation.
Microelectron. J.
Divya Duvvuri, Vijaya Sankara Rao Pasupureddi
2015 C conf
MIL-STD-1553+: Integrated remote terminal and bus controller at 100-Mb/s data rate.
ISCAS
Prateek Pendyala, Vijaya Sankara Rao Pasupureddi
2015 — conf
RT-MIL-STD-1553+: Remote terminal controller for MIL-STD-1553B at 100-Mb/s data rate.
ISQED
Prateek Pendyala, Vijaya Sankara Rao Pasupureddi
2014 — conf
100-Mbps transceiver for enhanced MIL-STD-1553.
APCCAS
Divya Duvvuri, Vijaya Sankara Rao Pasupureddi, J. Chattopadhyay
2014 — conf
A 5-Gb/s adaptive CTLE with eye-monitoring for multi-drop bus applications.
MWSCAS
Somanshu Agarwal, Vijaya Sankara Rao Pasupureddi
2014 Misc conf
A Low Power CMOS Imager Based on Distributed Compressed Sensing.
VLSID
Bhuvanan Kaliannan, Vijaya Sankara Rao Pasupureddi
2014 Misc conf
A Power Efficient Fully Differential Back Terminated Current-Mode HDMI Source.
VLSID
R. Gopikrishnan, Vijaya Sankara Rao Pasupureddi, Govindarajulu Regeti
2014 — conf
Design and simulation of a wideband channelized transceiver for DRFM applications.
APCCAS
Ajinkya Kale, Vijaya Sankara Rao Pasupureddi, J. Chattopadhyay
2013 C conf
A low-power area-efficient compressive sensing approach for multi-channel neural recording.
ISCAS
Mahsa Shoaran, Mariazel Maqueda Lopez, Vijaya Sankara Rao Pasupureddi, Yusuf Leblebici, Alexandre Schmid
2013 Misc conf
Implementation of a Charge Redistribution Based 2-D DCT Architecture for Wireless Capsule Endoscopy.
VLSI Design
Bhuvanan Kaliannan, Vijaya Sankara Rao Pasupureddi
2012 J jnl
A Low-Power 5-Gb/s Current-Mode LVDS Output Driver and Receiver with Active Termination.
Circuits Syst. Signal Process.
Vijaya Sankara Rao Pasupureddi, Nachiket V. Desai, Pradip Mandal
2012 J jnl
Active-terminated transmitter and receiver circuits for high-speed low-swing duobinary signaling.
Int. J. Circuit Theory Appl.
Vijaya Sankara Rao Pasupureddi, Pradip Mandal
2011 Misc conf
A New Double Data Rate(DDR) Dual-Mode Duobinary Transmitter Architecture.
VLSI Design
Mrigank Sharad, Vijaya Sankara Rao Pasupureddi, Pradip Mandal
2011 J jnl
Current-mode full-duplex (CMFD) signaling for high-speed chip-to-chip interconnect.
Microelectron. J.
Vijaya Sankara Rao Pasupureddi, Pradip Mandal
2010 — conf
A new power efficient current-mode 4-PAM transmitter interface for off-chip interconnect.
APCCAS
Vijaya Sankara Rao Pasupureddi, Pradip Mandal
2010 — conf
Current-mode echo cancellation for full-duplex chip-to-chip data communication.
APCCAS
Vijaya Sankara Rao Pasupureddi, Pradip Mandal
2009 — conf
High-Speed Low-Current Duobinary Signaling Over Active Terminated Chip-to-Chip Interconnect.
ISVLSI
Vijaya Sankara Rao Pasupureddi, Pradip Mandal, Sunil Sachdev
2008 Misc conf
Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design.
VLSI Design
T. Venkata Kalyan, Madhu Mutyam, Vijaya Sankara Rao Pasupureddi