Vijay Sundararajan

20 papers A* 2A 2Misc 3Journal 4Unranked 7
YearRankTypeTitle / Venue / Authors
2016 — ch.
Gate Sizing.
Encyclopedia of Algorithms
Vijay Sundararajan
2008 — ch.
Gate Sizing.
Encyclopedia of Algorithms
Vijay Sundararajan
2008 Misc conf
Optimal power allocation for sum capacity of a slotted three-cell system.
ICASSP
Vikram Chandrasekhar, Zukang Shen, Vijay Sundararajan
2004 J jnl
A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints.
ACM Trans. Design Autom. Electr. Syst.
Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
2003 J jnl
Synthesis of minimum-area folded architectures for rectangular multidimensional multirate DSP systems.
IEEE Trans. Signal Process.
Vijay Sundararajan, Keshab K. Parhi
2002 J jnl
Fast and exact transistor sizing based on iterative relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
2001 — conf
Energy Efficient Signaling in Deep Submicron CMOS Technology.
ISQED
Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi
2001 — conf
Energy efficient signaling in DSM CMOS technology.
ISCAS (5)
Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi
2001 J jnl
Vector processing of wavelet coefficients for robust image denoising.
Image Vis. Comput.
Michael E. Zervakis, Vijay Sundararajan, Keshab K. Parhi
2000 Misc conf
A novel multiply multiple accumulator component for low power PDSP design.
ICASSP
Vijay Sundararajan, Keshab K. Parhi
2000 — conf
Data transmission over a bus with peak-limited transition activity.
ASP-DAC
Vijay Sundararajan, Keshab K. Parhi
2000 A* conf
MINFLOTRANSIT: min-cost flow based transistor sizing tool.
DAC
Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
2000 — conf
Reducing bus transition activity by limited weight coding with codeword slimming.
ACM Great Lakes Symposium on VLSI
Vijay Sundararajan, Keshab K. Parhi
2000 — conf
Synthesis of low power folded programmable coefficient FIR digital filters (short paper).
ASP-DAC
Vijay Sundararajan, Keshab K. Parhi
1999 — conf
Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution.
ARVLSI
Vijay Sundararajan, Keshab K. Parhi
1999 A conf
Low power synthesis of dual threshold voltage CMOS VLSI circuits.
ISLPED
Vijay Sundararajan, Keshab K. Parhi
1999 A conf
Marsh: min-area retiming with setup and hold constraints.
ICCAD
Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
1999 A* conf
Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages.
DAC
Vijay Sundararajan, Keshab K. Parhi
1998 Misc conf
Synthesis of folded, pipelined architectures for multi-dimensional multirate systems.
ICASSP
Vijay Sundararajan, Keshab K. Parhi
1997 — conf
A Wavelet-Domain Algorithm for Denoising in the Presence of Noise Outliers.
ICIP (1)
Michael E. Zervakis, Vijay Sundararajan, Keshab K. Parhi