Vijay Gangaram

14 papers A 2B 1Misc 6Journal 2Unranked 3
YearRankTypeTitle / Venue / Authors
2018 A conf
Online Scan Diagnosis : A Novel Approach to Volume Diagnosis.
ITC
I-De Huang, Pallav Gupta, Loganathan Lingappan, Vijay Gangaram
2013 B conf
Test generation for circuits with embedded memories using SMT.
ETS
Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram
2012 Misc conf
A Novel SMT-Based Technique for LFSR Reseeding.
VLSI Design
Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram
2012 Misc conf
A SMT-based diagnostic test generation method for combinational circuits.
VTS
Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram
2011 — conf
An Efficient 2-Phase Strategy to Achieve High Branch Coverage.
Asian Test Symposium
Sarvesh Prabhu, Michael S. Hsiao, Saparya Krishnamoorthy, Loganathan Lingappan, Vijay Gangaram, Jim Grundy
2009 J jnl
Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha, Sreejit Chakravarty
2008 — conf
Efficient Selection of Observation Points for Functional Tests.
ISQED
Jian Kang, Sharad C. Seth, Yi-Shing Chang, Vijay Gangaram
2007 Misc conf
Efficient RTL Coverage Metric for Functional Test Selection.
VTS
Jian Kang, Sharad C. Seth, Vijay Gangaram
2007 Misc conf
Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits.
VLSI Design
Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha
2006 — conf
Functional Test Selection for High Volume Manufacturing.
MTV
Vijay Gangaram, Deepa Bhan, James K. Caldwell
2006 Misc conf
Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring.
VTS
Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram
1998 J jnl
A controller redesign technique to enhance testability of controller-data path circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sujit Dey, Vijay Gangaram, Miodrag Potkonjak
1997 Misc conf
Deriving Signal Constraints to Accelerate Sequential Test Generation.
VLSI Design
Srimat T. Chakradhar, Vijay Gangaram, Steven G. Rothweiler
1995 A conf
A controller-based design-for-testability technique for controller-data path circuits.
ICCAD
Sujit Dey, Vijay Gangaram, Miodrag Potkonjak