Victor V. Zyuban

38 papers A* 4A 10Journal 13Unranked 11

Year	Rank	Type	Title / Venue / Authors
2015	J	`jnl`	IBM POWER8 circuit design and energy optimization. IBM J. Res. Dev. Victor V. Zyuban, Joshua Friedrich, Daniel M. Dreps, Jürgen Pille, Donald W. Plass, Phillip J. Restle, Zeynep Toprak Deniz, Matthew M. Ziegler, Sam G. Chu, Md. Saiful Islam, James D. Warnock, Bob Philhower, Rahul M. Rao, Gregory S. Still, David Shan, Eric Fluhr, Jose Paredes, Dieter F. Wendel, Christopher J. Gonzalez, D. Hogenmiller, Ruchir Puri, Scott A. Taylor, Stephen D. Posluszny
2015	—	`conf`	Session 8 overview: Low-power digital techniques: Energy-efficient digital. ISSCC Victor V. Zyuban, Peter Nilsson
2015	J	`jnl`	The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. IEEE J. Solid State Circuits Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher J. Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip J. Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael A. Sperling, Kevin Stawiasz, Gregory S. Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban
2014	—	`conf`	5.1 POWER8 ISSCC Eric J. Fluhr, Joshua Friedrich, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, Allen Hall, David Hogenmiller, Frank Malgioglio, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Ruchir Puri, Phillip J. Restle, David Shan, Kevin Stawiasz, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler
2014	—	`conf`	POWER8 design methodology innovations for improving productivity and reducing power. CICC Matthew M. Ziegler, Ruchir Puri, Bob Philhower, Robert L. Franch, Wing K. Luk, Jens Leenstra, Peter Verwegen, Niels Fricke, George Gristede, Eric Fluhr, Victor V. Zyuban
2014	—	`conf`	The POWER8 ICICDT Joshua Friedrich, Hung Q. Le, William J. Starke, Jeff Stuecheli, Balaram Sinharoy, Eric J. Fluhr, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, David Hogenmiller, Frank Malgioglio, Ryan Nett, Ruchir Puri, Phillip J. Restle, David Shan, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler, Dave W. Victor
2013	A	`conf`	Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis. ICCAD Nagu R. Dhanwada, David J. Hathaway, Victor V. Zyuban, Peng Peng, Karl Moody, William W. Dungan, Arun Joseph, Rahul M. Rao, Christopher J. Gonzalez
2013	J	`jnl`	IBM POWER7+ design for higher frequency at fixed power. IBM J. Res. Dev. Victor V. Zyuban, Scott A. Taylor, Birger Christensen, A. R. Hall, Christopher J. Gonzalez, Joshua Friedrich, Frances Clougherty, Jon Tetzloff, Rajeev R. Rao
2013	A	`conf`	Power reduction by aggressive synthesis design space exploration. ISLPED Matthew M. Ziegler, George Gristede, Victor V. Zyuban
2013	J	`jnl`	Runtime power reduction capability of the IBM POWER7+ chip. IBM J. Res. Dev. Michael S. Floyd, Alan J. Drake, Nicole S. Schwartz, Robert W. Berry, Charles Lefurgy, Malcolm S. Ware, Karthick Rajamani, Victor V. Zyuban, Richard L. Willaman, Ruby M. Zgabay
2011	J	`jnl`	POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. IEEE J. Solid State Circuits Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott A. Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban
2010	—	`conf`	POWER7 ISSCC James D. Warnock, Leon J. Sigal, Dieter F. Wendel, K. Paul Muller, Joshua Friedrich, Victor V. Zyuban, Ethan H. Cannon, A. J. KleinOsowski
2010	—	`conf`	Power-efficient, reliable microprocessor architectures: modeling and design methods. ACM Great Lakes Symposium on VLSI Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor V. Zyuban
2010	—	`conf`	The implementation of POWER7 ISSCC Dieter F. Wendel, Ronald N. Kalla, Robert Cargnoni, Joachim G. Clabes, Joshua Friedrich, Roland Frech, James A. Kahle, Balaram Sinharoy, William J. Starke, Scott A. Taylor, Steve Weitzel, Sam G. Chu, Md. Saiful Islam, Victor V. Zyuban
2009	—	`conf`	A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR). PATMOS Milena Vratonjic, Matthew M. Ziegler, George Gristede, Victor V. Zyuban, Thomas Mitchell, Ee Cho, Chandu Visweswariah, Vojin G. Oklobdzija
2009	A	`conf`	The opportunity cost of low power design: a case study in circuit tuning. ISLPED Matthew M. Ziegler, Victor V. Zyuban, George Gristede, Milena Vratonjic, Joshua Friedrich
2008	A*	`conf`	A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime. ISCA Jeonghee Shin, Victor V. Zyuban, Pradip Bose, Timothy Mark Pinkston
2007	A	`conf`	A Framework for Architecture-Level Lifetime Reliability Modeling. DSN Jeonghee Shin, Victor V. Zyuban, Zhigang Hu, Jude A. Rivers, Pradip Bose
2005	A*	`conf`	Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling. ISCA Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen
2005	A*	`conf`	Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. HPCA Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler
2004	—	`conf`	Design methodology for semi custom processor cores. ACM Great Lakes Symposium on VLSI Victor V. Zyuban, Sameh W. Asaad, Thomas W. Fox, Anne-Marie Haen, Daniel Littrell, Jaime H. Moreno
2004	J	`jnl`	Integrated Analysis of Power and Performance for Pipelined Microprocessors. IEEE Trans. Computers Victor V. Zyuban, David M. Brooks, Viji Srinivasan, Michael Gschwind, Pradip Bose, Philip N. Strenski, Philip G. Emma
2004	A	`conf`	Microarchitectural techniques for power gating of execution units. ISLPED Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose
2003	J	`jnl`	An innovative low-power high-performance programmable signal processor for digital communications. IBM J. Res. Dev. Jaime H. Moreno, Victor V. Zyuban, Uzi Shvadron, Fredy D. Neeser, Jeff H. Derby, Malcolm S. Ware, Krishnan Kailas, Ayal Zaks, Amir B. Geva, Shay Ben-David, Sameh W. Asaad, Thomas W. Fox, Daniel Littrell, Marina Biberstein, Dorit Naishlos, Hillery C. Hunter
2003	J	`jnl`	Balancing hardware intensity in microprocessor pipelines. IBM J. Res. Dev. Victor V. Zyuban, Philip N. Strenski
2003	J	`jnl`	Low-power circuits and technology for wireless digital systems. IBM J. Res. Dev. Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin W. Warren, Victor V. Zyuban
2003	J	`jnl`	Optimization of scannable latches for low energy. IEEE Trans. Very Large Scale Integr. Syst. Victor V. Zyuban
2002	—	`conf`	Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. PACS Pradip Bose, David M. Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas
2002	A	`conf`	Low power integrated scan-retention mechanism. ISLPED Victor V. Zyuban, Stephen V. Kosonocky
2002	A*	`conf`	Optimizing pipelines for power and performance. MICRO Viji Srinivasan, David M. Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma
2002	—	`conf`	Unified architecture level energy-efficiency metric. ACM Great Lakes Symposium on VLSI Victor V. Zyuban
2002	A	`conf`	Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels. ISLPED Victor V. Zyuban, Philip N. Strenski
2001	A	`conf`	Clocking strategies and scannable latches for low power appliacations. ISLPED Victor V. Zyuban, David Meltzer
2001	J	`jnl`	Inherently Lower-Power High-Performance Superscalar Architectures. IEEE Trans. Computers Victor V. Zyuban, Peter M. Kogge
2000	A	`conf`	Optimization of high-performance superscalar architectures for energy efficiency. ISLPED Victor V. Zyuban, Peter M. Kogge
2000	J	`jnl`	Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors. IEEE Micro David M. Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook
1999	J	`jnl`	Application of STD to latch-power estimation. IEEE Trans. Very Large Scale Integr. Syst. Victor V. Zyuban, Peter M. Kogge
1998	A	`conf`	The energy complexity of register files. ISLPED Victor V. Zyuban, Peter M. Kogge