Venkatesh Akella

91 papers A* 7A 7B 5C 7Misc 6Journal 33Unranked 26

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Space-Control: Process-Level Isolation for Sharing CXL-based Disaggregated Memory. CoRR Kaustav Goswami, Sean Peisert, Venkatesh Akella, Jason Lowe-Power
2025	A*	`conf`	NOVA: A Novel Vertex Management Architecture for Scalable Graph Processing. HPCA Marjan Fariborz, Mahyar Samani, Austin York, S. J. Ben Yoo, Jason Lowe-Power, Venkatesh Akella
2025	—	`conf`	Precision Aware Bank Separated Data Placement. MEMSYS Divyansh Maura, Venkatesh Akella
2025	—	`conf`	TEGRA - Scaling Up Graph Processing with Disaggregated Computing. SC Workshops William Shaddix, Mahyar Samani, Jason Lowe-Power, Venkatesh Akella
2024	A	`conf`	CachedArrays: Optimizing Data Movement for Heterogeneous Memory Systems. IPDPS Mark Hildebrand, Jason Lowe-Power, Venkatesh Akella
2024	J	`jnl`	TEGRA - Scaling Up Terascale Graph Processing with Disaggregated Computing. CoRR William Shaddix, Mahyar Samani, Marjan Fariborz, S. J. Ben Yoo, Jason Lowe-Power, Venkatesh Akella
2023	C	`conf`	Efficient Large Scale DLRM Implementation on Heterogeneous Memory Systems. ISC Mark Hildebrand, Jason Lowe-Power, Venkatesh Akella
2023	Misc	`conf`	Scalable Hardware Acceleration of Graph Processing with Photonic Interconnects. PSC Venkatesh Akella, Marjan Fariborz, Mahyar Samani, S. J. Ben Yoo, Jason Lowe-Power
2022	J	`jnl`	A Model for Scalable and Balanced Accelerators for Graph Processing. IEEE Comput. Archit. Lett. Marjan Fariborz, Mahyar Samani, Terry O'Neill, Jason Lowe-Power, S. J. Ben Yoo, Venkatesh Akella
2022	C	`conf`	LLM: Realizing Low-Latency Memory by Exploiting Embedded Silicon Photonics for Irregular Workloads. ISC Marjan Fariborz, Mahyar Samani, Pouya Fotouhi, Roberto Proietti, Il-Min Yi, Venkatesh Akella, Jason Lowe-Power, Samuel Palermo, S. J. Ben Yoo
2022	—	`conf`	SoK: Limitations of Confidential Computing via TEEs for High-Performance Compute Systems. SEED Ayaz Akram, Venkatesh Akella, Sean Peisert, Jason Lowe-Power
2021	B	`conf`	A Case Against Hardware Managed DRAM Caches for NVRAM Based Systems. ISPASS Mark Hildebrand, Julian T. Angeles, Jason Lowe-Power, Venkatesh Akella
2021	C	`conf`	HTA: A Scalable High-Throughput Accelerator for Irregular HPC Workloads. ISC Pouya Fotouhi, Marjan Fariborz, Roberto Proietti, Jason Lowe-Power, Venkatesh Akella, S. J. Ben Yoo
2021	A	`conf`	Performance Analysis of Scientific Computing Workloads on General Purpose TEEs. IPDPS Ayaz Akram, Anna Giannakou, Venkatesh Akella, Jason Lowe-Power, Sean Peisert
2020	A*	`conf`	AutoTM: Automatic Tensor Movement in Heterogeneous Memory Systems using Integer Linear Programming. ASPLOS Mark Hildebrand, Jawad Khan, Sanjeev Trika, Jason Lowe-Power, Venkatesh Akella
2020	J	`jnl`	FPGA and GPU-based acceleration of ML workloads on Amazon cloud - A case study using gradient boosted decision tree library. Integr. Maxim Shepovalov, Venkatesh Akella
2020	B	`conf`	HCAPP: Scalable Power Control for Heterogeneous 2.5D Integrated Systems. ICPP Kramer Straube, Jason Lowe-Power, Christopher Nitta, Matthew K. Farrens, Venkatesh Akella
2020	J	`jnl`	Performance Analysis of Scientific Computing Workloads on Trusted Execution Environments. CoRR Ayaz Akram, Anna Giannakou, Venkatesh Akella, Jason Lowe-Power, Sean Peisert
2020	J	`jnl`	Predicting soil permanganate oxidizable carbon (POXC) by coupling DRIFT spectroscopy and artificial neural networks (ANN). Comput. Electron. Agric. Andrew Margenot, Terry O'Neill, Rolf Sommer, Venkatesh Akella
2019	J	`jnl`	Multiplier-Free Implementation of Galois Field Fourier Transform on a FPGA. IEEE Trans. Circuits Syst. II Express Briefs Sree Balaji Girisankar, Mona Nasseri, Jennifer Priscilla, Shu Lin, Venkatesh Akella
2018	—	`conf`	A case for exposing extra-architectural state in the ISA: position paper. HASP@ISCA Jason Lowe-Power, Venkatesh Akella, Matthew K. Farrens, Samuel T. King, Christopher J. Nitta
2018	Misc	`conf`	Improving Provisioned Power Efficiency in HPC Systems with GPU-CAPP. HiPC Kramer Straube, Jason Lowe-Power, Christopher Nitta, Matthew K. Farrens, Venkatesh Akella
2018	—	`conf`	Scalable Hardware Accelerator for Mini-Batch Gradient Descent. ACM Great Lakes Symposium on VLSI Sandeep Rasoori, Venkatesh Akella
2017	A*	`conf`	Design and Evaluation of AWGR-Based Photonic NoC Architectures for 2.5D Integrated High Performance Computing Systems. HPCA Paolo Grani, Roberto Proietti, Venkatesh Akella, S. J. Ben Yoo
2017	C	`conf`	Improving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power Processing. ICCD Kramer Straube, Christopher Nitta, Raj Amirtharajah, Matthew K. Farrens, Venkatesh Akella
2016	—	`conf`	Design space exploration of FPGA-based Deep Convolutional Neural Networks. ASP-DAC Mohammad Motamedi, Philipp Gysel, Venkatesh Akella, Soheil Ghiasi
2016	A*	`conf`	HogWild++: A New Mechanism for Decentralized Asynchronous Stochastic Gradient Descent. ICDM Huan Zhang, Cho-Jui Hsieh, Venkatesh Akella
2016	—	`conf`	Photonic Interconnects for Interposer-based 2.5D/3D Integrated Systems on a Chip. MEMSYS Paolo Grani, Roberto Proietti, Venkatesh Akella, S. J. Ben Yoo
2014	J	`jnl`	PDG_GEN: A Methodology for Fast and Accurate Simulation of On-Chip Networks. IEEE Trans. Computers Kevin Macdonald, Christopher Nitta, Matthew K. Farrens, Venkatesh Akella
2014	J	`jnl`	Runtime Adaptation of Applications Using Design Of Experiments: A Smartphone-Based Case Study. IEEE Embed. Syst. Lett. Frank Maker III, Rajeevan Amirtharajah, Venkatesh Akella
2014	J	`jnl`	Simultaneously Reducing Latency and Power Consumption in OpenFlow Switches. IEEE/ACM Trans. Netw. Paul Congdon, Prasant Mohapatra, Matthew K. Farrens, Venkatesh Akella
2013	J	`jnl`	MELOADES: Methodology for long-term online adaptation of embedded software for heterogeneous devices. J. Syst. Archit. Frank Maker III, Rajeevan Amirtharajah, Venkatesh Akella
2013	—	`conf`	Scalability and performance of a distributed AWGR-based all-optical token interconnect architecture. OFC/NFOEC Roberto Proietti, Christopher J. Nitta, Yawei Yin, Venkatesh Akella, S. J. Ben Yoo
2013	A	`conf`	Update rate tradeoffs for improving online power modeling in smartphones. ISLPED Frank Maker III, Rajeevan Amirtharajah, Venkatesh Akella
2012	J	`jnl`	AWGR-Based Optical Topologies for Scalable and Efficient Global Communications in Large-Scale Multi-Processor Systems. JOCN Xiaohui Ye, S. J. Ben Yoo, Venkatesh Akella
2012	A	`conf`	DCAF - A Directly Connected Arbitration-Free Photonic Crossbar for Energy-Efficient High Performance Computing. IPDPS Christopher Nitta, Matthew K. Farrens, Venkatesh Akella
2012	J	`jnl`	DCOF - An Arbitration Free Directly Connected Optical Fabric. IEEE J. Emerg. Sel. Topics Circuits Syst. Christopher Nitta, Matthew K. Farrens, Venkatesh Akella
2012	J	`jnl`	Efficient Configurable Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. Xiaoheng Chen, Shu Lin, Venkatesh Akella
2011	A*	`conf`	Addressing system-level trimming issues in on-chip nanophotonic networks. HPCA Christopher Nitta, Matthew K. Farrens, Venkatesh Akella
2011	J	`jnl`	Buffering and Flow Control in Optical Switches for High Performance Computing. JOCN Xiaohui Ye, Roberto Proietti, Yawei Yin, S. J. Ben Yoo, Venkatesh Akella
2011	J	`jnl`	Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA. ACM Trans. Reconfigurable Technol. Syst. Xiaoheng Chen, Venkatesh Akella
2011	J	`jnl`	Hardware Implementation of a Backtracking-Based Reconfigurable Decoder for Lowering the Error Floor of Quasi-Cyclic LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella
2011	—	`conf`	Inferring packet dependencies to improve trace based simulation of on-chip networks. NOCS Christopher Nitta, Kevin Macdonald, Matthew K. Farrens, Venkatesh Akella
2011	J	`jnl`	Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella
2011	A*	`conf`	Resilient microring resonator based photonic networks. MICRO Christopher Nitta, Matthew K. Farrens, Venkatesh Akella
2010	—	`conf`	DOS: a scalable optical switch for datacenters. ANCS Xiaohui Ye, Yawei Yin, S. J. Ben Yoo, Paul Vincent Mejia, Roberto Proietti, Venkatesh Akella
2010	J	`jnl`	Markov decision process (MDP) framework for software power optimization using call profiles on mobile phones. Des. Autom. Embed. Syst. Eric Jung, Frank Maker III, Tang Lung Cheung, Xin Liu, Venkatesh Akella
2010	J	`jnl`	Optical Router Control Architecture and Contention Resolution Algorithms Capable of Asynchronous, Variable-Length Packet Switching. JOCN Haijun Yang, Zhong Pan, Venkatesh Akella, Chen-Nee Chuah, S. J. Ben Yoo
2010	—	`conf`	Performance Evaluation of a Multicore System with Optically Connected Memory Modules. NOCS Paul Vincent Mejia, Rajeevan Amirtharajah, Matthew K. Farrens, Venkatesh Akella
2010	J	`jnl`	QSN - A Simple Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders. IEEE Trans. Circuits Syst. II Express Briefs Xiaoheng Chen, Shu Lin, Venkatesh Akella
2009	A	`conf`	Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing. DATE Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella
2009	—	`conf`	FPGA-based low-complexity high-throughput tri-mode decoder for quasi-cyclic LDPC codes. Allerton Xiaoheng Chen, Qin Huang, Shu Lin, Venkatesh Akella
2009	Misc	`conf`	Markov decision process (MDP) framework for optimizing software on mobile phones. EMSOFT Tang Lung Cheung, Kari Okamoto, Frank Maker III, Xin Liu, Venkatesh Akella
2008	—	`conf`	Credit-based dynamic reliability management using online wearout detection. Conf. Computing Frontiers John Y. Oliver, Rajeevan Amirtharajah, Venkatesh Akella, Frederic T. Chong
2008	C	`conf`	Design and evaluation of an optical CPU-DRAM interconnect. ICCD Amit Hadke, Tony Benavides, Rajeevan Amirtharajah, Matthew K. Farrens, Venkatesh Akella
2008	—	`conf`	OCDIMM: Scaling the DRAM Memory Wall Using WDM Based Optical Interconnects. Hot Interconnects Amit Hadke, Tony Benavides, S. J. Ben Yoo, Rajeevan Amirtharajah, Venkatesh Akella
2007	J	`jnl`	Life Cycle Aware Computing: Reusing Silicon Technology. Computer John Y. Oliver, Rajeevan Amirtharajah, Venkatesh Akella, Roland Geyer, Frederic T. Chong
2007	J	`jnl`	Using Application Bisection Bandwidth to Guide Tile Size Selection for the Synchroscalar Tile-Based Architecture. Trans. High Perform. Embed. Archit. Compil. John Y. Oliver, Diana Franklin, Frederic T. Chong, Venkatesh Akella
2006	Misc	`conf`	Segmented Bitline Cache: Exploiting Non-uniform Memory Access Patterns. HiPC Ravishankar Rao, Justin Wenck, Diana Franklin, Rajeevan Amirtharajah, Venkatesh Akella
2006	J	`jnl`	Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications. J. Embed. Comput. John Y. Oliver, Ravishankar Rao, Diana Franklin, Frederic T. Chong, Venkatesh Akella
2006	—	`conf`	Tile size selection for low-power tile-based architectures. Conf. Computing Frontiers John Y. Oliver, Ravishankar Rao, Michael Brown, Jennifer Mankin, Diana Franklin, Frederic T. Chong, Venkatesh Akella
2005	—	`conf`	Complexity metric driven energy optimization framework for implementing MPEG-21 scalable video decoders. ICASSP (2) Gouri Landge, Mihaela van der Schaar, Venkatesh Akella
2005	—	`conf`	Generic modeling of complexity for motion-compensated wavelet video decoders. Electronic Imaging: Image and Video Communications and Processing Gouri Landge, Mihaela van der Schaar, Venkatesh Akella
2005	A	`conf`	Proactive Energy Optimization Algorithms for Wavelet-Based Video Codecs on Power-Aware Processors. ICME Venkatesh Akella, Mihaela van der Schaar, Wen-Fu Kao
2005	—	`conf`	Scheduling optical packets in wavelength, time, and space domains for all-optical packet switching routers. ICC Haijun Yang, Venkatesh Akella, Chen-Nee Chuah, S. J. Ben Yoo
2004	B	`conf`	Efficient orchestration of sub-word parallelism in media processors. SPAA John Y. Oliver, Venkatesh Akella, Frederic T. Chong
2004	B	`conf`	Rate-distortion-complexity adaptive video compression and streaming. ICIP Mihaela van der Schaar, Deepak S. Turaga, Venkatesh Akella
2004	A*	`conf`	Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor. ISCA John Y. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong
2003	J	`jnl`	High-performance optical-label switching packet routers and smart edge routers for the next-generation Internet. IEEE J. Sel. Areas Commun. S. J. Ben Yoo, Fei Xue, Yash Bansal, Julie Taylor, Zhong Pan, Jing Cao, Min-Yong Jeon, Tony Nady, Gary Goncher, Kirk Boyer, Kari Okamoto, Shin Kamei, Venkatesh Akella
2003	B	`conf`	Improving DSP Performance with a Small Amount of Field Programmable Logic. FPL John Y. Oliver, Venkatesh Akella
2003	—	`conf`	Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture. PACS John Y. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Dean Copsey, Diana Keen, Venkatesh Akella, Frederic T. Chong
2001	—	`conf`	An Asynchronous Superscalar Architecture for Exploiting Instruction-Level Parallelism. ASYNC Tony Werner, Venkatesh Akella
1999	Misc	`conf`	Automatic Insertion of Gated Clocks at Register Transfer Level. VLSI Design Nithya Raghavan, Venkatesh Akella, Smita Bakshi
1998	J	`jnl`	Asynchronous Comparison-Based Decoders for Delay-Insensitive Codes. IEEE Trans. Computers Venkatesh Akella, Nitin H. Vaidya, G. Robert Redinbo
1998	J	`jnl`	Micropipelined asynchronous discrete cosine transform (DCT/IDCT) processor. IEEE Trans. Very Large Scale Integr. Syst. Dave Johnson, Venkatesh Akella, Bret Stott
1997	J	`jnl`	Asynchronous Processor Survey. Computer Tony Werner, Venkatesh Akella
1996	—	`conf`	Counterflow pipeline based dynamic instruction scheduling. ASYNC Tony Werner, Venkatesh Akella
1996	—	`conf`	Limitations of VLSI Implementation of Delay-Insensitive Codes. FTCS Venkatesh Akella, Nitin H. Vaidya, G. Robert Redinbo
1995	C	`conf`	Asynchronous 2-D discrete cosine transform core processor. ICCD Bret Stott, Dave Johnson, Venkatesh Akella
1994	—	`conf`	A technique for estimating power in asynchronous circuits. ASYNC Prabhakar Kudva, Venkatesh Akella
1994	J	`jnl`	CFSIM: A Concurrent Compiled Code Functional Simulator for hopCP. Int. J. Comput. Simul. Venkatesh Akella, Ganesh Gopalakrishnan
1994	J	`jnl`	High-level optimizations in compiling process descriptions to asynchronous circuits. J. VLSI Signal Process. Ganesh Gopalakrishnan, Venkatesh Akella
1994	C	`conf`	Performance Analysis and Optimization of Asynchronous Circuits. ICCD Prabhakar Kudva, Ganesh Gopalakrishnan, Erik Brunvand, Venkatesh Akella
1994	J	`jnl`	Specification and Validation of Control-Intensive IC's in hopCP. IEEE Trans. Software Eng. Venkatesh Akella, Ganesh Gopalakrishnan
1994	—	`conf`	Testing two-phase transition signaling based self-timed circuits in a synthesis environment. HLSS Prabhakar Kudva, Venkatesh Akella
1993	—	`conf`	A transformational approach to asynchronous high-level synthesis. VLSI Ganesh Gopalakrishnan, Venkatesh Akella
1992	Misc	`conf`	From Process-Oriented Functional Specifications to Efficient Asynchronous Circuits. VLSI Design Venkatesh Akella, Ganesh Gopalakrishnan
1992	A	`conf`	SHILPA: a high-level synthesis system for self-timed circuits. ICCAD Venkatesh Akella, Ganesh Gopalakrishnan
1992	J	`jnl`	VLSI asynchronous systems: specification and synthesis. Microprocess. Microsystems Ganesh Gopalakrishnan, Venkatesh Akella
1989	J	`jnl`	HOP: A process model for synchronous hardware; semantics and experiments in process composition. Integr. Ganesh Gopalakrishnan, Richard M. Fujimoto, Venkatesh Akella, Narayana Mani
1989	—	`conf`	Parallel Composition of Lockstep Synchronous Processes for Hardware Validation: Divide-and-Conquer Composition. Automatic Verification Methods for Finite State Systems Ganesh Gopalakrishnan, Narayana Mani, Venkatesh Akella