Venkataraman Mahalingam

15 papers A 1C 2Misc 1Journal 6Unranked 5
YearRankTypeTitle / Venue / Authors
2012 J jnl
Dynamic clock stretching for variation compensation in VLSI circuit design.
ACM J. Emerg. Technol. Comput. Syst.
Venkataraman Mahalingam, Nagarajan Ranganathan, Ransford Hyman Jr.
2010 J jnl
A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation.
IEEE Trans. Very Large Scale Integr. Syst.
Venkataraman Mahalingam, Koustav Bhattacharya, N. Ranganathan, Hari Chakravarthula, Robin R. Murphy, Kevin S. Pratt
2010 J jnl
Timing-Based Placement Considering Uncertainty Due to Process Variations.
IEEE Trans. Very Large Scale Integr. Syst.
Venkataraman Mahalingam, N. Ranganathan
2009 C conf
A VLSI System Architecture for Optical Flow Computation.
ISCAS
Koustav Bhattacharya, Venkataraman Mahalingam, Nagarajan Ranganathan
2009 J jnl
Variation-aware multimetric optimization during gate sizing.
ACM Trans. Design Autom. Electr. Syst.
Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam
2008 — conf
A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing.
ISVLSI
Venkataraman Mahalingam, Nagarajan Ranganathan
2008 J jnl
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing.
IEEE Trans. Very Large Scale Integr. Syst.
Venkataraman Mahalingam, N. Ranganathan, J. E. Harlow
2008 — conf
Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty.
ACM Great Lakes Symposium on VLSI
N. Ranganathan, Upavan Gupta, Venkataraman Mahalingam
2007 — conf
Variation Aware Timing Based Placement Using Fuzzy Programming.
ISQED
Venkataraman Mahalingam, N. Ranganathan
2006 A conf
A novel approach for variation aware power minimization during gate sizing.
ISLPED
Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III
2006 Misc conf
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition.
VLSI Design
Venkataraman Mahalingam, N. Ranganathan
2006 J jnl
Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition.
IEEE Trans. Computers
Venkataraman Mahalingam, Nagarajan Ranganathan
2005 — conf
A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection.
ISVLSI
Venkataraman Mahalingam, N. Ranganathan
2004 — conf
Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design.
DELTA
N. Venkateswaran, V. Barath Kumar, R. Raghavan, R. Srinivas, S. Subramanian, V. Balaji, Venkataraman Mahalingam, T. L. Rajaprabhu
2003 C conf
Analysis of Bit Transition Count for EDAC Encoded FSM.
IOLTS
N. Venkateswaran, V. Balaji, Venkataraman Mahalingam, T. L. Rajaprabhu