Venkata Naveen Kolakaluri

14 papers C 3Journal 5Unranked 6

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 49.23% Power Reduction Active Gate Driver with Digital Multi-level Power Gating Control. J. Circuits Syst. Comput. Chua-Chin Wang, Pradyumna Vellanki, Soumika Majumder, L. S. S. Pavan Kumar Chodisetti, Venkata Naveen Kolakaluri, Mitch Ming-Chi Chou, Lean Karlo Santos Tolentino
2025	J	`jnl`	A 24.9% Power Reduction Active Gate Driver With Power Gating and Current Modulation for Power MOSFETs. IEEE Trans. Circuits Syst. II Express Briefs Chua-Chin Wang, Pradyumna Vellanki, Wei-En Chiu, L. S. S. Pavan Kumar Chodisetti, Venkata Naveen Kolakaluri, Yun-Che Chang, Mitch Ming-Chi Chou
2025	J	`jnl`	A Power Transistor Active Gate Driver With Two-Level Miller Plateau Detection and Driving Device Equalization Using 180-nm HV BCD Process. IEEE Open J. Circuits Syst. Chua-Chin Wang, Pradyumna Vellanki, Venkata Naveen Kolakaluri, L. S. S. Pavan Kumar Chodisetti, Lean Karlo Santos Tolentino, Mitch Ming-Chi Chou, Oliver Lexter July Alvarez Jose
2025	J	`jnl`	Up To 99.6 % duty cycle digital PWM using 180-nm CMOS process. Microelectron. J. Chua-Chin Wang, Oliver Lexter July Alvarez Jose, Venkata Naveen Kolakaluri
2024	C	`conf`	A 10-MHz 5-V On-chip 6-layer Multi-level Digital Transformer Using T18HVG2 Process. ISCAS Oliver Lexter July A. Jose, Yun-Che Chang, Venkata Naveen Kolakaluri, Celso B. Co, Mitch Ming-Chi Chou, Chua-Chin Wang
2024	J	`jnl`	A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array. IEEE Trans. Very Large Scale Integr. Syst. Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Chua-Chin Wang
2024	—	`conf`	A Multi-Level Power Gating Logic Controlled Driver for A 10-V Power Transistor Using 180-nm High Voltage BCD Process. ISOCC Soumika Majumder, Lean Karlo Santos Tolentino, Oliver Lexter July Alvarez Jose, Venkata Naveen Kolakaluri, Mitch Ming-Chi Chou, Chua-Chin Wang
2024	C	`conf`	A Wide Range 2-to-2048 Division Ratio Frequency Divider Using 40-nm CMOS Process. ISCAS Soumika Majumder, Venkata Naveen Kolakaluri, Oliver Lexter July A. Jose, Chua-Chin Wang
2024	—	`conf`	Active Gate Driver Design Using Differential Timing-based Miller Detector for Power MOSFET. APCCAS Pradyumna Vellanki, Venkata Naveen Kolakaluri, Yun-Che Chang, L. S. S. Pavan Kumar Chodisetti, Mitch Ming-Chi Chou, Chua-Chin Wang
2023	—	`conf`	2-Level Miller Detection-Based High Side Gate Driver Design for Power MOSFETs. APCCAS Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Jui-Min Kuo, Mitch Ming-Chi Chou, Chua-Chin Wang
2023	—	`conf`	A 99.6 % Duty Cycle High-Resolution DPWM Using Reconfiguring Decoder. MWSCAS Venkata Naveen Kolakaluri, Oliver Lexter July A. Jose, Chua-Chin Wang
2023	C	`conf`	Matrix Phase Shift Based DPWM Technique To Achieve 90% Duty Cycle. ISCAS Venkata Naveen Kolakaluri, Oliver Lexter July A. Jose, Chua-Chin Wang
2023	—	`conf`	SiC MOSFET High Side Gate Driver Design Using HV CMOS Process. MWSCAS Oliver Lexter July A. Jose, Jui-Min Kuo, Venkata Naveen Kolakaluri, Chua-Chin Wang
2022	—	`conf`	A Novel Constant-pulse Scheme for Synchronous Half-bridge Converter Module. APCCAS Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Chua-Chin Wang