Vaughn Betz - RankMe

155 papers A 28B 30Misc 9Journal 54Unranked 32

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Corrigendum: VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration. ACM Trans. Reconfigurable Technol. Syst. Mohamed A. Elgammal, Amin Mohaghegh, Soheil Gholami Shahrouz, Fatemehsadat Mahmoudi, Fahrican Kosar, Kimia Talaei, Joshua Fife, Daniel Khadivi, Kevin E. Murray, Andrew Boutros, Kenneth B. Kent, Jeffrey B. Goeders, Vaughn Betz
2025	B	`conf`	Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage. FPL Junius Pun, Xilai Dai, Grace Zgheib, Mahesh A. Iyer, Andrew Boutros, Vaughn Betz, Mohamed S. Abdelfattah
2025	J	`jnl`	Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage. CoRR Junius Pun, Xilai Dai, Grace Zgheib, Mahesh A. Iyer, Andrew Boutros, Vaughn Betz, Mohamed S. Abdelfattah
2025	J	`jnl`	Editorial: A Message from the New Editor-in-Chief. ACM Trans. Reconfigurable Technol. Syst. Vaughn Betz
2025	J	`jnl`	Field-Programmable Gate Array Architecture for Deep Learning: Survey and Future Directions. Proc. IEEE Andrew Boutros, Aman Arora, Vaughn Betz
2025	B	`conf`	From Errors to Solutions: LLM-Powered Command Scripting for FPGA Cad Tools. FPL Mohamed A. Elgammal, Vaughn Betz
2025	J	`jnl`	VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration. ACM Trans. Reconfigurable Technol. Syst. Mohamed A. Elgammal, Amin Mohaghegh, Soheil Gholami Shahrouz, Fatemehsadat Mahmoudi, Fahrican Kosar, Kimia Talaei, Joshua Fife, Daniel Khadivi, Kevin E. Murray, Andrew Boutros, Kenneth B. Kent, Jeffrey B. Goeders, Vaughn Betz
2024	B	`conf`	A Software-Programmable Neural Processing Unit for Graph Neural Network Inference on FPGAs. FPL Taikun Zhang, Andrew Boutros, Sergey Gribok, Kwadwo Boateng, Vaughn Betz
2024	B	`conf`	Better Together: Combining Analytical and Annealing Methods for FPGA Placement. FPL Rachel Selina Rajarathnam, Kate Thurmer, Vaughn Betz, Mahesh A. Iyer, David Z. Pan
2024	J	`jnl`	Field-Programmable Gate Array Architecture for Deep Learning: Survey & Future Directions. CoRR Andrew Boutros, Aman Arora, Vaughn Betz
2024	B	`conf`	H2PIPE: High Throughput CNN Inference on FPGAs with High-Bandwidth Memory. FPL Mario Doumet, Marius Stan, Mathew Hall, Vaughn Betz
2024	J	`jnl`	H2PIPE: High throughput CNN Inference on FPGAs with High-Bandwidth Memory. CoRR Mario Doumet, Marius Stan, Mathew Hall, Vaughn Betz
2024	J	`jnl`	High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design. ACM Trans. Reconfigurable Technol. Syst. Anupreetham Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-sun Seo
2024	—	`conf`	Multiqueue-Based FPGA Routing: Relaxed A* Priority Ordering for Improved Parallelism. ICFPT Alexandre Singer, Hang Yan, Guozheng Zhang, Mark C. Jeffrey, Mirjana Stojilovic, Vaughn Betz
2024	—	`conf`	Parallel FPGA Routing with On-The-Fly Net Decomposition. ICFPT Fahrican Kosar, Mirjana Stojilovic, Vaughn Betz
2024	Misc	`conf`	Stay Flexible: A High-Performance FPGA NPU Overlay for Graph Neural Networks. FCCM Taikun Zhang, Andrew Boutros, Sergey Gribok, Kwadwo Boateng, Vaughn Betz
2024	B	`conf`	The Road Less Traveled: Congestion-Aware NoC Placement and Packet Routing for FPGAs. FPL Soheil Gholami Shahrouz, Vaughn Betz
2024	—	`conf`	VIPER: A VTR Interface for Placement with Error Resilience. HEART Kate Thurmer, Vaughn Betz
2023	B	`conf`	A Whole New World: How to Architect Beyond-FPGA Reconfigurable Acceleration Devices? FPL Andrew Boutros, Stephen More, Vaughn Betz
2023	—	`conf`	Breaking Boundaries: Optimizing FPGA CAD with Flexible and Multi-threaded Re-Clustering. HEART Mohamed A. Elgammal, Vaughn Betz
2023	—	`conf`	Extending Data Flow Architectures for Convolutional Neural Networks to Multiple FPGAs. ICFPT Mohamed Ibrahim, Zhipeng Zhao, Mathew Hall, Vaughn Betz
2023	—	`conf`	Into the Third Dimension: Architecture Exploration Tools for 3D Reconfigurable Acceleration Devices. ICFPT Andrew Boutros, Fatemehsadat Mahmoudi, Amin Mohaghegh, Stephen More, Vaughn Betz
2023	J	`jnl`	Koios 2.0: Open-Source Deep Learning Benchmarks for FPGA Architecture and CAD Research. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Aman Arora, Andrew Boutros, Seyed Alireza Damghani, Karan Mathur, Vedant Mohanty, Tanmay Anand, Mohamed A. Elgammal, Kenneth B. Kent, Vaughn Betz, Lizy K. John
2023	A	`conf`	Open-source and FPGAs: Hardware, Software, Both or None? FPGA Dana How, Tim Ansell, Vaughn Betz, Chris Lavin, Ted Speers, Pierre-Emmanuel Gaillardon
2023	Misc	`conf`	Placement Optimization for NoC-Enhanced FPGAs. FCCM Srivatsan Srinivasan, Andrew Boutros, Fatemehsadat Mahmoudi, Vaughn Betz
2023	J	`jnl`	RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices. CoRR Andrew Boutros, Eriko Nurvitadhi, Vaughn Betz
2023	—	`conf`	Respect the Difference: Reinforcement Learning for Heterogeneous FPGA Placement. ICFPT Fatemehsadat Mahmoudi, Mohamed A. Elgammal, Soheil Gholami Shahrouz, Kevin E. Murray, Vaughn Betz
2023	B	`conf`	Tear Down The Wall: Unified and Efficient Intra-and Inter-Cluster Routing for FPGAs. FPL Amin Mohaghegh, Vaughn Betz
2023	B	`conf`	Titan 2.0: Enabling Open-Source CAD Evaluation with a Modern Architecture Capture. FPL Kimia Talaei Khoozani, Arash Ahmadian Dehkordi, Vaughn Betz
2023	J	`jnl`	Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-Simulation. ACM Trans. Reconfigurable Technol. Syst. Sameh Attia, Vaughn Betz
2023	B	`conf`	VPR-Gym: A Platform for Exploring AI Techniques in FPGA Placement Optimization. FPL Ruichen Chen, Shengyao Lu, Mohamed A. Elgammal, Peter Chun, Vaughn Betz, Di Niu
2023	—	`conf`	cuSCNN : an Efficient CUDA Implementation of Sparse CNNs. HEART Mohamed A. Elgammal, Omar Mohamed Awad, Isak Edo Vivancos, Andreas Moshovos, Vaughn Betz
2022	J	`jnl`	Architecture and Application Co-Design for Beyond-FPGA Reconfigurable Acceleration Devices. IEEE Access Andrew Boutros, Eriko Nurvitadhi, Vaughn Betz
2022	—	`conf`	HPIPE NX: Boosting CNN Inference Acceleration Performance with AI-Optimized FPGAs. FPT Marius Stan, Mathew Hall, Mohamed Ibrahim, Vaughn Betz
2022	—	`conf`	Quality & Generality: A Flexible FPGA Re-Clustering Technique to Improve Packing and Placement. FPT Mohamed A. Elgammal, Vaughn Betz
2022	B	`conf`	RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices. FPL Andrew Boutros, Eriko Nurvitadhi, Vaughn Betz
2022	J	`jnl`	RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mohamed A. Elgammal, Kevin E. Murray, Vaughn Betz
2022	J	`jnl`	Stop and Look: A Novel Checkpointing and Debugging Flow for FPGAs. IEEE Trans. Computers Sameh Attia, Vaughn Betz
2022	J	`jnl`	Tensor Slices: FPGA Building Blocks For The Deep Learning Era. ACM Trans. Reconfigurable Technol. Syst. Aman Arora, Moinak Ghosh, Samidh Mehta, Vaughn Betz, Lizy K. John
2021	B	`conf`	End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression. FPL Anupreetham Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-sun Seo
2021	B	`conf`	Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research. FPL Aman Arora, Andrew Boutros, Daniel Rauch, Aishwarya Rajen, Aatman Borda, Seyed Alireza Damghani, Samidh Mehta, Sangram Kate, Pragnesh Patel, Kenneth B. Kent, Vaughn Betz, Lizy K. John
2021	J	`jnl`	Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research. CoRR Aman Arora, Andrew Boutros, Daniel Rauch, Aishwarya Rajen, Aatman Borda, Seyed Alireza Damghani, Samidh Mehta, Sangram Kate, Pragnesh Patel, Kenneth B. Kent, Vaughn Betz, Lizy K. John
2021	J	`jnl`	Optimizing Interstitial Photodynamic Therapy Planning With Reinforcement Learning-Based Diffuser Placement. IEEE Trans. Biomed. Eng. Abdul-Amir Yassine, Lothar Lilge, Vaughn Betz
2021	—	`conf`	Specializing for Efficiency: Customizing AI Inference Processors on FPGAs. ICM Andrew Boutros, Eriko Nurvitadhi, Vaughn Betz
2021	—	`conf`	StateLink: FPGA System Debugging via Flexible Simulation/Hardware Integration. FPT Sameh Attia, Vaughn Betz
2021	A	`conf`	Tensor Slices to the Rescue: Supercharging ML Acceleration on FPGAs. FPGA Aman Arora, Samidh Mehta, Vaughn Betz, Lizy K. John
2020	—	`conf`	AIR: A Fast but Lazy Timing-Driven FPGA Router. ASP-DAC Kevin E. Murray, Sheng Zhong, Vaughn Betz
2020	—	`conf`	Beyond Peak Performance: Comparing the Real Performance of AI-Optimized FPGAs and GPUs. FPT Andrew Boutros, Eriko Nurvitadhi, Rui Ma, Sergey Gribok, Zhipeng Zhao, James C. Hoe, Vaughn Betz, Martin Langhammer
2020	J	`jnl`	FPGA Logic Block Architectures for Efficient Deep Learning Inference. ACM Trans. Reconfigurable Technol. Syst. Mohamed Eldafrawy, Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz
2020	J	`jnl`	Feel Free to Interrupt: Safe Task Stopping to Enable FPGA Checkpointing and Context Switching. ACM Trans. Reconfigurable Technol. Syst. Sameh Attia, Vaughn Betz
2020	—	`conf`	From TensorFlow Graphs to LUTs and Wires: Automated Sparse and Physically Aware CNN Hardware Generation. FPT Mathew Hall, Vaughn Betz
2020	A	`conf`	HPIPE: Heterogeneous Layer-Pipelined and Sparse-Aware CNN Inference for FPGAs. FPGA Mathew Hall, Vaughn Betz
2020	J	`jnl`	HPIPE: Heterogeneous Layer-Pipelined and Sparse-Aware CNN Inference for FPGAs. CoRR Mathew Hall, Vaughn Betz
2020	—	`conf`	Learn to Place: FPGA Placement Using Reinforcement Learning and Directed Moves. FPT Mohamed A. Elgammal, Kevin E. Murray, Vaughn Betz
2020	—	`conf`	Neighbors From Hell: Voltage Attacks Against Deep Learning Accelerators on Multi-Tenant FPGAs. FPT Andrew Boutros, Mathew Hall, Nicolas Papernot, Vaughn Betz
2020	J	`jnl`	Neighbors From Hell: Voltage Attacks Against Deep Learning Accelerators on Multi-Tenant FPGAs. CoRR Andrew Boutros, Mathew Hall, Nicolas Papernot, Vaughn Betz
2020	J	`jnl`	Optimizing FPGA Logic Block Architectures for Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. Kevin E. Murray, Jason Luu, Matthew J. P. Walker, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
2020	J	`jnl`	Optimizing FPGA Logic Circuitry for Variable Voltage Supplies. IEEE Trans. Very Large Scale Integr. Syst. Ibrahim Ahmed, Linda L. Shen, Vaughn Betz
2020	A	`conf`	StateMover: Combining Simulation and Hardware Execution for Efficient FPGA Debugging. FPGA Sameh Attia, Vaughn Betz
2020	—	`conf`	StateReveal: Enabling Checkpointing of FPGA Designs with Buried State. FPT Sameh Attia, Vaughn Betz
2020	J	`jnl`	SymbiFlow and VPR: An Open-Source Design Flow for Commercial and Novel FPGAs. IEEE Micro Kevin E. Murray, Mohamed A. Elgammal, Vaughn Betz, Tim Ansell, Keith Rothman, Alessandro Comodi
2020	A	`conf`	Using OpenCL to Enable Software-like Development of an FPGA-Accelerated Biophotonic Cancer Treatment Simulator. FPGA Tanner Young-Schultz, Lothar Lilge, Stephen Brown, Vaughn Betz
2020	J	`jnl`	VTR 8: High-performance CAD and Customizable FPGA Architecture Modelling. ACM Trans. Reconfigurable Technol. Syst. Kevin E. Murray, Oleg Petelin, Sheng Zhong, Jia Min Wang, Mohamed Eldafrawy, Jean-Philippe Legault, Eugene Sha, Aaron Graham, Jean Wu, Matthew J. P. Walker, Hanqing Zeng, Panagiotis Patros, Jason Luu, Kenneth B. Kent, Vaughn Betz
2019	B	`conf`	Becoming More Tolerant: Designing FPGAs for Variable Supply Voltage. FPL Ibrahim Ahmed, Linda L. Shen, Vaughn Betz
2019	J	`jnl`	COFFE 2: Automatic Modelling and Optimization of Complex and Heterogeneous FPGA Architectures. ACM Trans. Reconfigurable Technol. Syst. Sadegh Yazdanshenas, Vaughn Betz
2019	J	`jnl`	Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kevin E. Murray, Andrea Suardi, Vaughn Betz, George A. Constantinides
2019	J	`jnl`	FRoC 2.0: Automatic BRAM and Logic Testing to Enable Dynamic Voltage Scaling for FPGA Applications. ACM Trans. Reconfigurable Technol. Syst. Ibrahim Ahmed, Shuze Zhao, James Meijers, Olivier Trescases, Vaughn Betz
2019	Misc	`conf`	Fast Voltage Transients on FPGAs: Impact and Mitigation Strategies. FCCM Linda L. Shen, Ibrahim Ahmed, Vaughn Betz
2019	A	`conf`	Math Doesn't Have to be Hard: Logic Block Architectures to Enhance Low-Precision Multiply-Accumulate on FPGAs. FPGA Andrew Boutros, Mohamed Eldafrawy, Sadegh Yazdanshenas, Vaughn Betz
2019	Misc	`conf`	Safe Task Interruption for FPGAs. FCCM Sameh Attia, Vaughn Betz
2019	J	`jnl`	The Costs of Confidentiality in Virtualized FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Sadegh Yazdanshenas, Vaughn Betz
2018	Misc	`conf`	A High-Level Synthesis Case Study on Light Propagation Simulation in Turbid Media. FCCM Abdul-Amir Yassine, Yasmin Afsharnejad, Omar Ragheb, Vaughn Betz, Paul Chow
2018	J	`jnl`	Automatic Application-Specific Calibration to Enable Dynamic Voltage Scaling in FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ibrahim Ahmed, Shuze Zhao, Olivier Trescases, Vaughn Betz
2018	B	`conf`	Automatic BRAM Testing for Robust Dynamic Voltage Scaling for FPGAs. FPL Ibrahim Ahmed, Shuze Zhao, James Meijers, Olivier Trescases, Vaughn Betz
2018	B	`conf`	Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs. FPL Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz
2018	J	`jnl`	Enhancing FPGAs with Magnetic Tunnel Junction-Based Block RAMs. ACM Trans. Reconfigurable Technol. Syst. Kosuke Tatsumura, Sadegh Yazdanshenas, Vaughn Betz
2018	J	`jnl`	Frequency-Domain Power Delivery Network Self-Characterization in FPGAs for Improved System Reliability. IEEE Trans. Ind. Electron. Shuze Zhao, Ibrahim Ahmed, Vaughn Betz, Ashraf Lotfi, Olivier Trescases
2018	—	`conf`	HLS-based FPGA Acceleration of Light Propagation Simulation in Turbid Media. HEART Yasmin Afsharnejad, Abdul-Amir Yassine, Omar Ragheb, Paul Chow, Vaughn Betz
2018	J	`jnl`	High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft Processors. ACM Trans. Reconfigurable Technol. Syst. Henry Wong, Vaughn Betz, Jonathan Rose
2018	—	`conf`	Improving Confidentiality in Virtualized FPGAs. FPT Sadegh Yazdanshenas, Vaughn Betz
2018	J	`jnl`	Interconnect Solutions for Virtualized Field-Programmable Gate Arrays. IEEE Access Sadegh Yazdanshenas, Vaughn Betz
2018	B	`conf`	Latency Insensitive Design Styles for FPGAs. FPL Mustafa Abbas, Vaughn Betz
2018	—	`conf`	Tatum: Parallel Timing Analysis for Faster Design Cycles and Improved Optimization. FPT Kevin E. Murray, Vaughn Betz
2018	J	`jnl`	Wotan: Evaluating FPGA Architecture Routability without Benchmarks. ACM Trans. Reconfigurable Technol. Syst. Oleg Petelin, Vaughn Betz
2018	J	`jnl`	You Cannot Improve What You Do not Measure: FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference. ACM Trans. Reconfigurable Technol. Syst. Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz
2017	—	`conf`	Automatic circuit design and modelling for heterogeneous FPGAs. FPT Sadegh Yazdanshenas, Vaughn Betz
2017	J	`jnl`	Design and Applications for Embedded Networks-on-Chip on FPGAs. IEEE Trans. Computers Mohamed S. Abdelfattah, Andrew Bitar, Vaughn Betz
2017	A	`conf`	Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration. FPGA Sadegh Yazdanshenas, Kosuke Tatsumura, Vaughn Betz
2017	B	`conf`	Find the real speed limit: FPGA CAD for chip-specific application delay measurement. FPL Ibrahim Ahmed, Shuze Zhao, Olivier Trescases, Vaughn Betz
2017	B	`conf`	Quantifying and mitigating the costs of FPGA virtualization. FPL Sadegh Yazdanshenas, Vaughn Betz
2017	A	`conf`	Quantifying error: Extending static timing analysis with probabilistic transitions. DATE Kevin E. Murray, Andrea Suardi, Vaughn Betz, George A. Constantinides
2016	Misc	`conf`	High Performance Instruction Scheduling Circuits for Out-of-Order Soft Processors. FCCM Henry Wong, Vaughn Betz, Jonathan Rose
2016	—	`conf`	High density, low energy, magnetic tunnel junction based block RAMs for memory-rich FPGAs. FPT Kosuke Tatsumura, Sadegh Yazdanshenas, Vaughn Betz
2016	B	`conf`	LYNX: CAD for FPGA-based networks-on-chip. FPL Mohamed S. Abdelfattah, Vaughn Betz
2016	B	`conf`	Measure twice and cut once: Robust dynamic voltage scaling for FPGAs. FPL Ibrahim Ahmed, Shuze Zhao, Olivier Trescases, Vaughn Betz
2016	J	`jnl`	Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System. ACM Trans. Reconfigurable Technol. Syst. Henry Wong, Vaughn Betz, Jonathan Rose
2016	J	`jnl`	Multiple Dice Working as One: CAD Flows and Routing Architectures for Silicon Interposer FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Ehsan Nasiri, Javeed Shaikh, André Hahn Pereira, Vaughn Betz
2016	J	`jnl`	Power Analysis of Embedded NoCs on FPGAs and Comparison With Custom Buses. IEEE Trans. Very Large Scale Integr. Syst. Mohamed S. Abdelfattah, Vaughn Betz
2016	B	`conf`	The speed of diversity: Exploring complex FPGA routing topologies for the global metal layer. FPL Oleg Petelin, Vaughn Betz
2015	—	`conf`	Bringing programmability to the data plane: Packet processing with a NoC-enhanced FPGA. FPT Andrew Bitar, Mohamed S. Abdelfattah, Vaughn Betz
2015	B	`conf`	Design and simulation tools for Embedded NOCs on FPGAs. FPL Mohamed S. Abdelfattah, Andrew Bitar, Ange Yaghi, Vaughn Betz
2015	—	`conf`	HETRIS: Adaptive floorplanning for heterogeneous FPGAs. FPT Kevin E. Murray, Vaughn Betz
2015	J	`jnl`	Robust Optimization of Multiple Timing Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michael Wainberg, Vaughn Betz
2015	A	`conf`	Take the Highway: Design for Embedded NoCs on FPGAs. FPGA Mohamed S. Abdelfattah, Andrew Bitar, Vaughn Betz
2015	J	`jnl`	Timing-Driven Titan: Enabling Large Benchmarks and Exploring the Gap between Academic and Commercial CAD. ACM Trans. Reconfigurable Technol. Syst. Kevin E. Murray, Scott Whitty, Suya Liu, Jason Luu, Vaughn Betz
2015	B	`conf`	Wotan: A tool for rapid evaluation of FPGA architecture routability without benchmarks. FPL Oleg Petelin, Vaughn Betz
2014	A	`conf`	Cad and routing architecture for interposer-based multi-FPGA systems. FPGA André Hahn Pereira, Vaughn Betz
2014	—	`conf`	Comparing performance, productivity and scalability of the TILT overlay processor to OpenCL HLS. FPT Rafat Rashid, J. Gregory Steffan, Vaughn Betz
2014	—	`conf`	Efficient and programmable ethernet switching with a NoC-enhanced FPGA. ANCS Andrew Bitar, Jeffrey Cassidy, Natalie D. Enright Jerger, Vaughn Betz
2014	Misc	`conf`	Fast, Power-Efficient Biophotonic Simulations for Cancer Treatment Using FPGAs. FCCM Jeffrey Cassidy, Lothar Lilge, Vaughn Betz
2014	J	`jnl`	Networks-on-Chip for FPGAs: Hard, Soft or Mixed? ACM Trans. Reconfigurable Technol. Syst. Mohamed S. Abdelfattah, Vaughn Betz
2014	Misc	`conf`	On Hard Adders and Carry Chains in FPGAs. FCCM Jason Luu, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
2014	J	`jnl`	Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design. IEEE Trans. Very Large Scale Integr. Syst. Henry Wong, Vaughn Betz, Jonathan Rose
2014	A	`conf`	Quantifying the cost and benefit of latency insensitive communication on FPGAs. FPGA Kevin E. Murray, Vaughn Betz
2014	Misc	`conf`	Speeding Up FPGA Placement: Parallel Algorithms and Methods. FCCM Matthew An, J. Gregory Steffan, Vaughn Betz
2014	A	`ed.`	The 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, Monterey, CA, USA - February 26 - 28, 2014 FPGA Vaughn Betz, George A. Constantinides
2014	J	`jnl`	The Case for Embedded Networks on Chip on Field-Programmable Gate Arrays. IEEE Micro Mohamed S. Abdelfattah, Vaughn Betz
2014	J	`jnl`	VTR 7.0: Next Generation Architecture and CAD System for FPGAs. ACM Trans. Reconfigurable Technol. Syst. Jason Luu, Jeffrey Goeders, Michael Wainberg, Andrew Somerville, Thien Yu, Konstantin Nasartschuk, Miad Nasr, Sen Wang, Tim Liu, Nooruddin Ahmed, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
2013	A	`conf`	Are FPGAs suffering from the innovator's dilemna? FPGA Vaughn Betz, Jason Cong
2013	—	`conf`	COFFE: Fully-automated transistor sizing for FPGAs. FPT Charles Chiasson, Vaughn Betz
2013	—	`conf`	Efficient methods for out-of-order load/store execution for high-performance soft processors. FPT Henry Wong, Vaughn Betz, Jonathan Rose
2013	B	`conf`	From Quartus to VPR: Converting HDL to BLIF with the Titan flow. FPL Kevin E. Murray, Scott Whitty, Suya Liu, Jason Luu, Vaughn Betz
2013	B	`conf`	Should FPGAS abandon the pass-gate? FPL Charles Chiasson, Vaughn Betz
2013	A	`ed.`	The 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '13, Monterey, CA, USA, February 11-13, 2013 FPGA Brad L. Hutchings, Vaughn Betz
2013	B	`conf`	The power of communication: Energy-efficient NOCS for FPGAS. FPL Mohamed S. Abdelfattah, Vaughn Betz
2013	B	`conf`	Titan: Enabling large and complex benchmarks in academic CAD. FPL Kevin E. Murray, Scott Whitty, Suya Liu, Jason Luu, Vaughn Betz
2012	—	`conf`	Design tradeoffs for hard and soft FPGA-based Networks-on-Chip. FPT Mohamed S. Abdelfattah, Vaughn Betz
2012	J	`jnl`	Portable and scalable FPGA-based acceleration of a direct linear system solver. ACM Trans. Reconfigurable Technol. Syst. Wei Zhang, Vaughn Betz, Jonathan Rose
2011	A	`conf`	Comparing FPGA vs. custom cmos and the impact on processor microarchitecture. FPGA Henry Wong, Vaughn Betz, Jonathan Rose
2011	J	`jnl`	Efficient and Deterministic Parallel Placement for FPGAs. ACM Trans. Design Autom. Electr. Syst. Adrian Ludwin, Vaughn Betz
2011	J	`jnl`	FPGAs, Programming Models, and Kit Cars. IEEE Des. Test Comput. Vaughn Betz
2010	A	`conf`	A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs. FPGA Doris Chen, Deshanand P. Singh, Jeffrey Chromczak, David M. Lewis, Ryan Fung, David Neto, Vaughn Betz
2010	—	`conf`	Recent FPGA Advances and Challenges. ERSA Vaughn Betz, Stephen Brown
2009	—	`ch.`	FPGA Synthesis and Physical Design. Embedded Systems Design and Verification Mike Hutton, Vaughn Betz
2009	B	`conf`	FPGA challenges and opportunities at 40nm and beyond. FPL Vaughn Betz
2008	A	`conf`	High-quality, deterministic parallel placement for FPGAs on commodity hardware. FPGA Adrian Ludwin, Vaughn Betz, Ketan Padalia
2008	—	`conf`	Portable and scalable FPGA-based acceleration of a direct linear system solver. FPT Wei Zhang, Vaughn Betz, Jonathan Rose
2008	J	`jnl`	Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ryan Fung, Vaughn Betz, William Chow
2007	J	`jnl`	Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Russell Tessier, Vaughn Betz, David Neto, Aaron Egier, Thiagaraja Gopalsamy
2006	A	`conf`	Power-aware RAM mapping for FPGA embedded memory blocks. FPGA Russell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy
2005	A	`conf`	The Stratix II logic and routing architecture. FPGA David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose
2004	A	`conf`	Simultaneous short-path and long-path timing optimization for FPGAs. ICCAD Ryan Fung, Vaughn Betz, William Chow
2003	A	`conf`	The Stratix FPGA David M. Lewis, Vaughn Betz, David Jefferson, Andy Lee, Christopher Lane, Paul Leventis, Sandy Marquardt, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose
2000	A	`conf`	Automatic generation of FPGA routing architectures from high-level descriptions. FPGA Vaughn Betz, Jonathan Rose
2000	J	`jnl`	Speed and area tradeoffs in cluster-based FPGA architectures. IEEE Trans. Very Large Scale Integr. Syst. Alexander Marquardt, Vaughn Betz, Jonathan Rose
2000	A	`conf`	Timing-driven placement for FPGAs. FPGA Alexander Marquardt, Vaughn Betz, Jonathan Rose
1999	—	`book`	Architecture and CAD for Deep-Submicron FPGAS Vaughn Betz, Jonathan Rose, Alexander Marquardt
1999	A	`conf`	FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density. FPGA Vaughn Betz, Jonathan Rose
1999	A	`conf`	Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density. FPGA Alexander Marquardt, Vaughn Betz, Jonathan Rose
1998	A	`conf`	A Fast Routability-Driven Router for FPGAs. FPGA Jordan S. Swartz, Vaughn Betz, Jonathan Rose
1998	J	`jnl`	Effect of the prefabricated routing track distribution on FPGA area-efficiency. IEEE Trans. Very Large Scale Integr. Syst. Vaughn Betz, Jonathan Rose
1998	J	`jnl`	How Much Logic Should Go in an FPGA Logic Block? IEEE Des. Test Comput. Vaughn Betz, Jonathan Rose
1997	B	`conf`	VPR: A new packing, placement and routing tool for FPGA research. FPL Vaughn Betz, Jonathan Rose
1996	A	`conf`	Directional bias and non-uniformity in FPGA global routing architectures. ICCAD Vaughn Betz, Jonathan Rose
1995	A	`conf`	Using Architectural "Families" to Increase FPGA Speed and Density. FPGA Vaughn Betz, Jonathan Rose