Vassilis Papaefstathiou

56 papers A* 5A 7B 1C 2Misc 1Journal 20Unranked 19

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack. ACM Trans. Reconfigurable Technol. Syst. Manolis Ploumidis, Fabien Chaix, Nikolaos Chrysos, Marios Assiminakis, Nikolaos D. Kallimanis, Nikolaos Kossifidis, Michael Nikoloudakis, Nikolaos Dimou, Michalis Gianioudis, George Ieronymakis, Aggelos Ioannou, George Kalokerinos, Pantelis Xirouchakis, Astrinos Damianakis, Michael Ligerakis, Theocharis Vavouris, Manolis Katevenis, Vassilis Papaefstathiou, Manolis Marazakis, Iakovos Mavroidis
2024	C	`conf`	Low-latency Communication in RISC-V Clusters. HPC Asia Michalis Gianioudis, Pantelis Xirouchakis, Charisios Loukas, Evangelos Mageiropoulos, Orestis Mousouros, Sokratis Mpartzis, Aggelos Ioannou, Vassilis Papaefstathiou, Manolis Katevenis, Nikolaos Chrysos
2023	—	`conf`	Short Reasons for Long Vectors in HPC CPUs: A Study Based on RISC-V. SC Workshops Pablo Vizcaino, Georgios Ieronymakis, Nikolaos Dimou, Vassilis Papaefstathiou, Jesús Labarta, Filippo Mantovani
2023	J	`jnl`	Short reasons for long vectors in HPC CPUs: a study based on RISC-V. CoRR Pablo Vizcaino, Georgios Ieronymakis, Nikolaos Dimou, Vassilis Papaefstathiou, Jesús Labarta, Filippo Mantovani
2023	—	`conf`	Software Development Vehicles to Enable Extended and Early Co-design: A RISC-V and HPC Case of Study. ISC Workshops Filippo Mantovani, Pablo Vizcaino, Fabio Banchelli, Marta Garcia-Gasulla, Roger Ferrer, Georgios Ieronymakis, Nikolaos Dimou, Vassilis Papaefstathiou, Jesús Labarta
2023	J	`jnl`	Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study. CoRR Filippo Mantovani, Pablo Vizcaino, Fabio Banchelli, Marta Garcia-Gasulla, Roger Ferrer, Giorgos Ieronymakis, Nikos Dimou, Vassilis Papaefstathiou, Jesús Labarta
2023	J	`jnl`	The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack. CoRR Manolis Ploumidis, Fabien Chaix, Nikolaos Chrysos, Marios Asiminakis, Vassilis Flouris, Nikolaos D. Kallimanis, Nikolaos Kossifidis, Michael Nikoloudakis, Polydoros Petrakis, Nikolaos Dimou, Michalis Gianioudis, Georgios Ieronymakis, Aggelos Ioannou, George Kalokerinos, Pantelis Xirouchakis, Georgios Ailamakis, Astrinos Damianakis, Michael Ligerakis, Ioannis Makris, Theocharis Vavouris, Manolis Katevenis, Vassilis Papaefstathiou, Manolis Marazakis, Iakovos Mavroidis
2023	—	`conf`	eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem. CF Lluc Alvarez, Abraham Ruiz, Arnau Bigas-Soldevilla, Pavel Kuroedov, Alberto González, Hamsika Mahale, Noe Bustamante, Albert Aguilera, Francesco Minervini, Javier Salamero, Oscar Palomar, Vassilis Papaefstathiou, Antonis Psathakis, Nikolaos Dimou, Michalis Giaourtas, Iasonas Mastorakis, Georgios Ieronymakis, Georgios-Michail Matzouranis, Vassilis Flouris, Nick Kossifidis, Manolis Marazakis, Bhavishya Goel, Madhavan Manivannan, Ahsen Ejaz, Panagiotis Strikos, Mateo Vázquez, Ioannis Sourdis, Pedro Trancoso, Per Stenström, Jens Hagemeyer, Lennart Tigges, Nils Kucza, Jean-Marc Philippe, Ioannis Papaefstathiou
2022	J	`jnl`	Optimized Page Fault Handling During RDMA. IEEE Trans. Parallel Distributed Syst. Antonis Psistakis, Nikos Chrysos, Fabien Chaix, Marios Asiminakis, Michalis Gianioudis, Pantelis Xirouchakis, Vassilis Papaefstathiou, Manolis Katevenis
2021	J	`jnl`	HighwayNoC: Approaching Ideal NoC Performance With Dual Data Rate Routers. IEEE/ACM Trans. Netw. Ahsen Ejaz, Vassilis Papaefstathiou, Ioannis Sourdis
2021	—	`conf`	Multilevel simulation-based co-design of next generation HPC microprocessors. PMBS Lilia Zaourar, Mohamed Benazouz, Ayoub Mouhagir, Fatma Jebali, Tanguy Sassolas, Jean-Christophe Weill, Carlos Falquez, Nam Ho, Dirk Pleiter, Antoni Portero, Estela Suarez, Polydoros Petrakis, Vassilis Papaefstathiou, Manolis Marazakis, Milan Radulovic, Francesc Martínez, Adrià Armejach, Marc Casas, Alejandro Nocua, Romain Dolbeau
2020	A*	`conf`	Hybrid2: Combining Caching and Migration in Hybrid Memory Systems. HPCA Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis
2020	J	`jnl`	On Architectural Support for Instruction Set Randomization. ACM Trans. Archit. Code Optim. George Christou, Giorgos Vasiliadis, Vassilis Papaefstathiou, Antonis Papadogiannakis, Sotiris Ioannidis
2020	—	`conf`	PART: Pinning Avoidance in RDMA Technologies. NOCS Antonis Psistakis, Nikos Chrysos, Fabien Chaix, Marios Asiminakis, Michalis Giannioudis, Pantelis Xirouchakis, Vassilis Papaefstathiou, Manolis Katevenis
2020	J	`jnl`	Performance and Energy Footprint Assessment of FPGAs and GPUs on HPC Systems Using Astrophysics Application. Comput. David Goz, Georgios Ieronymakis, Vassilis Papaefstathiou, Nikolaos Dimou, Sara Bertocco, Francesco Simula, Antonio Ragagnin, Luca Tornatore, Igor Coretti, Giuliano Taffoni
2020	J	`jnl`	Performance and energy footprint assessment of FPGAs and GPUs on HPC systems using Astrophysics application. CoRR David Goz, Georgios Ieronymakis, Vassilis Papaefstathiou, Nikolaos Dimou, Sara Bertocco, Giuliano Taffoni, Francesco Simula, Antonio Ragagnin, Luca Tornatore, Igor Coretti
2020	J	`jnl`	Proceedings of the Thirteenth International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2020). CoRR Miquel Pericàs, Oscar Palomar, Vassilis Papaefstathiou, Mahmoud Eljammaly
2019	J	`jnl`	Decoupled Fused Cache: Fusing a Decoupled LLC with a DRAM Cache. ACM Trans. Archit. Code Optim. Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis
2019	—	`conf`	Direct N-Body Application on Low-Power and Energy-Efficient Parallel Architectures. PARCO Georgios Ieronymakis, Vassilis Papaefstathiou, Nikolaos Dimou, Sara Bertocco, Antonio Ragagnin, Luca Tornatore, Giuliano Taffoni, Igor Coretti
2019	J	`jnl`	Direct N-body application on low-power and energy-efficient parallel architectures. CoRR David Goz, Giorgos Ieronymakis, Vassilis Papaefstathiou, Nikolaos Dimou, Sara Bertocco, Antonio Ragagnin, Luca Tornatore, Giuliano Taffoni, Igor Coretti
2019	—	`conf`	Implementation and Impact of an Ultra-Compact Multi-FPGA Board for Large System Prototyping. H2RC@SC Fabien Chaix, Georgios Ailamakis, Theocharis Vavouris, Astrinos Damianakis, Manolis Katevenis, Iakovos Mavroidis, Aggelos Ioannou, Nikolaos Kossifidis, Nikolaos Dimou, Giorgos Ieronymakis, Manolis Marazakis, Vassilis Papaefstathiou, Vassilis Flouris, Mihailis Ligerakis
2019	A	`conf`	LLC-Guided Data Migration in Hybrid Memory Systems. IPDPS Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis
2019	J	`jnl`	Prototyping a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability. Trans. High Perform. Embed. Archit. Compil. George Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis G. Kavadias, Xiaojun Yang, Dionisios N. Pnevmatikatos, Manolis Katevenis
2019	—	`conf`	Software and Hardware Co-design for Low-Power HPC Platforms. ISC Workshops Manolis Ploumidis, Nikolaos D. Kallimanis, Marios Asiminakis, Nikos Chrysos, Pantelis Xirouchakis, Michalis Gianoudis, Leandros Tzanakis, Nikolaos Dimou, Antonis Psistakis, Panagiotis Peristerakis, Giorgos Kalokairinos, Vassilis Papaefstathiou, Manolis Katevenis
2018	A	`conf`	FusionCache: Using LLC tags for DRAM cache. DATE Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis
2018	J	`jnl`	Global Dead-Block Management for Task-Parallel Programs. ACM Trans. Archit. Code Optim. Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström
2018	A*	`conf`	ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness. HPCA Dmitry Knyaginin, Vassilis Papaefstathiou, Per Stenström
2017	—	`conf`	Modeling energy-performance tradeoffs in ARM big.LITTLE architectures. PATMOS Evangelos Vasilakis, Ioannis Sourdis, Vassilis Papaefstathiou, Antonis Psathakis, Manolis G. H. Katevenis
2017	—	`conf`	Odd-ECC: on-demand DRAM error correcting codes. MEMSYS Alirad Malek, Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis
2017	J	`jnl`	Runtime-Assisted Global Cache Management for Task-Based Parallel Programs. IEEE Comput. Archit. Lett. Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström
2017	J	`jnl`	SLOOP: QoS-Supervised Loop Execution to Reduce Energy on Heterogeneous Architectures. ACM Trans. Archit. Code Optim. Muhammad Waqar Azhar, Per Stenström, Vassilis Papaefstathiou
2016	—	`conf`	Adaptive Row Addressing for Cost-Efficient Parallel Memory Protocols in Large-Capacity Memories. MEMSYS Dmitry Knyaginin, Vassilis Papaefstathiou, Per Stenström
2016	A	`conf`	ECOSCALE: Reconfigurable computing and runtime system for future exascale systems. DATE Iakovos Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno, Dimitrios S. Nikolopoulos, Dirk Koch, John Goodacre, Ioannis Sourdis, Vassilis Papaefstathiou, Marcello Coppola, Manuel Palomino
2016	A*	`conf`	RADAR: Runtime-assisted dead region management for last-level caches. HPCA Madhavan Manivannan, Vassilis Papaefstathiou, Miquel Pericàs, Per Stenström
2015	—	`conf`	A Systematic Evaluation of Emerging Mesh-like CMP NoCs. ANCS Antonis Psathakis, Vassilis Papaefstathiou, Nikolaos Chrysos, Fabien Chaix, Evangelos Vasilakis, Dionisios N. Pnevmatikatos, Manolis Katevenis
2014	—	`—`	Architectural support for software-guided energy reduction of manycore communication Vassilis Papaefstathiou
2014	—	`conf`	Design space exploration for fair resource-allocated NoC architectures. ICSAMOS Antonis Psathakis, Vassilis Papaefstathiou, Manolis Katevenis, Dionisios N. Pnevmatikatos
2014	—	`conf`	Design trade-offs in energy efficient NoC architectures. NOCS Antonis Psathakis, Vassilis Papaefstathiou, Manolis Katevenis, Dionisios N. Pnevmatikatos
2014	J	`jnl`	FPGA prototyping of emerging manycore architectures for parallel programming research using Formic boards. J. Syst. Archit. Spyros Lyberis, George Kalokerinos, Michalis Lygerakis, Vassilis Papaefstathiou, Iakovos Mavroidis, Manolis Katevenis, Dionisios N. Pnevmatikatos, Dimitrios S. Nikolopoulos
2013	A*	`conf`	ASIST: architectural support for instruction set randomization. CCS Antonis Papadogiannakis, Laertis Loutsis, Vassilis Papaefstathiou, Sotiris Ioannidis
2013	J	`jnl`	NP-SARC: Scalable network processing in the SARC multi-core FPGA platform. J. Syst. Archit. Christoforos Kachris, George Nikiforos, Vassilis Papaefstathiou, Stamatis G. Kavadias, Manolis Katevenis
2013	A	`conf`	Prefetching and cache management using task lifetimes. ICS Vassilis Papaefstathiou, Manolis Katevenis, Dimitrios S. Nikolopoulos, Dionisios N. Pnevmatikatos
2012	Misc	`conf`	Formic: Cost-efficient and Scalable Prototyping of Manycore Architectures. FCCM Spyros Lyberis, George Kalokerinos, Michalis Lygerakis, Vassilis Papaefstathiou, Dimitrios Tsaliagkos, Manolis Katevenis, Dionisios N. Pnevmatikatos, Dimitrios S. Nikolopoulos
2011	A	`conf`	Fine-grain OpenMP runtime support with explicit communication hardware primitives. DATE Pranav Tendulkar, Vassilis Papaefstathiou, George Nikiforos, Stamatis G. Kavadias, Dimitrios S. Nikolopoulos, Manolis Katevenis
2010	J	`jnl`	Explicit Communication and Synchronization in SARC. IEEE Micro Manolis Katevenis, Vassilis Papaefstathiou, Stamatis G. Kavadias, Dionisios N. Pnevmatikatos, Federico Silla, Dimitrios S. Nikolopoulos
2010	—	`conf`	Network Processing in Multi-core FPGAs with Integrated Cache-Network Interface. ReConFig Christoforos Kachris, George Nikiforos, Stamatis G. Kavadias, Vassilis Papaefstathiou, Manolis Katevenis
2009	—	`conf`	FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability. ICSAMOS George Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis G. Kavadias, Manolis Katevenis, Dionisios N. Pnevmatikatos, Xiaojun Yang
2007	A*	`conf`	Memory-Efficient 5D Packet Classification At 40 Gbps. INFOCOM Ioannis Papaefstathiou, Vassilis Papaefstathiou
2007	A	`conf`	Optimization and bottleneck analysis of network block I/O in commodity storage systems. ICS Manolis Marazakis, Vassilis Papaefstathiou, Angelos Bilas
2007	—	`conf`	Prototyping Efficient Interprocessor Communication Mechanisms. ICSAMOS Vassilis Papaefstathiou, Dionisios N. Pnevmatikatos, Manolis Marazakis, Giorgos Kalokairinos, Aggelos Ioannou, Michael Papamichael, Stamatis G. Kavadias, Giorgos Mihelogiannakis, Manolis Katevenis
2006	—	`conf`	A hardware-engine for layer-2 classification in low-storage, ultra-high bandwidth environments. DATE Designers' Forum Vassilis Papaefstathiou, Ioannis Papaefstathiou
2006	—	`conf`	An innovative low-cost Classification Scheme for combined multi-Gigabit IP and Ethernet Networks. ICC Ioannis Papaefstathiou, Vassilis Papaefstathiou
2006	A	`conf`	Efficient remote block-level I/O over an RDMA-capable NIC. ICS Manolis Marazakis, Konstantinos Xinidis, Vassilis Papaefstathiou, Angelos Bilas
2006	C	`conf`	Experiences from Debugging a PCIX-based RDMA-capable NIC. CLUSTER Manolis Marazakis, Vassilis Papaefstathiou, Giorgos Kalokairinos, Angelos Bilas
2005	B	`conf`	A Memory Efficient, 100 Gb/sec MAC Classification Engine. LCN Vassilis Papaefstathiou, Ioannis Papaefstathiou
2004	J	`jnl`	Design-space exploration of the most widely used cryptography algorithms. Microprocess. Microsystems Ioannis Papaefstathiou, Vassilis Papaefstathiou, Christos P. Sotiriou