Vassilis Paliouras

158 papers A 2B 5C 28Misc 4Journal 26Unranked 91

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	A Mixed-Precision RNS DNN Accelerator. ISCAS Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas, Hani Saleh, Thanos Stouraitis
2025	—	`conf`	Design and Implementation of a Low-Complexity Neural Detector for Correlated Noise. SiPS Emmanouil Kavvousanos, Vassilis Paliouras
2025	J	`jnl`	Enhancing 5G Downlink Positioning Security: Embedding a Novel Authentication Scheme Into Empty PRS Resource Elements. IEEE Commun. Lett. Thodoris Spanos, Nikolaos Papageorgiou, Vassilis Paliouras
2025	B	`conf`	Evaluating Beam Sweeping for AoA Estimation with an RIS Prototype: Indoor/Outdoor Field Trials. WCNC Dimitris Vordonis, Dimitris Kompostiotis, Vassilis Paliouras, George C. Alexandropoulos, Florin Grec
2025	J	`jnl`	Evaluating Beam Sweeping for AoA Estimation with an RIS Prototype: Indoor/Outdoor Field Trials. CoRR Dimitris Vordonis, Dimitris Kompostiotis, Vassilis Paliouras, George C. Alexandropoulos, Florin Grec
2025	—	`conf`	Novel Scheduling and Shifter Networks for 5G LDPC Decoders. DASIP Nikos Papageorgiou, Vassilis Paliouras
2025	B	`conf`	Optimizing Indoor RIS-Aided Physical Layer Security: A Codebook-Generation Methodology and Measurement-Based Analysis. PIMRC Dimitris Kompostiotis, Dimitris Vordonis, Vassilis Paliouras, George C. Alexandropoulos
2025	B	`conf`	Theoretical and Experimental Evaluation of AoA Estimation in Single-Anchor 5G Uplink Positioning. PIMRC Thodoris Spanos, Fran Fabra, José A. López-Salcedo, Gonzalo Seco-Granados, Nikos Kanistras, Ivan Lapin, Vassilis Paliouras
2024	J	`jnl`	A Multiplier-Free RNS-Based CNN Accelerator Exploiting Bit-Level Sparsity. IEEE Trans. Emerg. Top. Comput. Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas, Hani Saleh, Thanos Stouraitis
2024	—	`conf`	An end-to-end RNS CNN Accelerator. AICAS Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas, Hani Saleh, Thanos Stouraitis
2024	—	`conf`	Angle of Arrival Estimation Using SRS in 5G NR Uplink Scenarios. WIPHAL Thodoris Spanos, Fran Fabra, José A. Lopez-Salcedo, Gonzalo Seco-Granados, Nikos Kanistras, Ivan Lapin, Vassilis Paliouras
2024	J	`jnl`	Evaluation of RIS-Enabled B5G/6G Indoor Positioning and Mapping using Ray Tracing Models. CoRR Dimitris Kompostiotis, Dimitris Vordonis, Vassilis Paliouras, George C. Alexandropoulos, Florin Grec
2024	A	`conf`	SECURED for Health: Scaling Up Privacy to Enable the Integration of the European Health Data Space. DATE Francesco Regazzoni, Gergely Ács, Albert Zoltan Aszalos, Christos Avgerinos, Nikolaos Bakalos, Josep Lluis Berral, Joppe W. Bos, Marco Brohet, Andrés G. Castillo Sanz, Gareth T. Davies, Stefanos Florescu, Pierre-Elisée Flory, Alberto Gutierrez-Torre, Evangelos Haleplidis, Alice Héliou, Sotirios Ioannidis, Alexander Islam El-Kady, Katarzyna Kapusta, Konstantina Karagianni, Pieter Kruizinga, Kyrian Maat, Zoltán Ádám Mann, Kalliopi Mastoraki, SeoJeong Moon, Maja Nisevic, Balázs Pejó, Kostas Papagiannopoulos, Vassilis Paliouras, Paolo Palmieri, Francesca Palumbo, Juan Carlos Pérez Baun, Péter Pollner, Eduard Porta-Pardo, Luca Pulina, Muhammad Ali Siddiqi, Daniela Spajic, Christos Strydis, Georgios Tasopoulos, Vincent Thouvenot, Christos Tselios, Apostolos P. Fournaris
2024	—	`conf`	Secrecy Rate Maximization in MIMO RIS-Aided Wireless Communications: A Hardware Accelerator Implementation for Reflection Optimization. SiPS Dimitris Kompostiotis, Vassilis Paliouras
2024	J	`jnl`	USRP-Based Single Anchor Positioning: AoA with 5G Uplink Signals, and UWB Ranging. CoRR Thodoris Spanos, Fran Fabra, José A. Lopez-Salcedo, Gonzalo Seco-Granados, Nikos Kanistras, Ivan Lapin, Vassilis Paliouras
2023	—	`conf`	A Regularization Approach to Maximize Common Sub-Expressions in Neural Network Weights. ICECS Emmanouil Kavvousanos, Ioannis Kouretas, Vassilis Paliouras, Thanos Stouraitis
2023	C	`conf`	A multiplier-Free RNS-Based CNN accelerator exploiting bit-Level sparsity. ARITH Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas, Hani Saleh, Thanos Stouraitis
2023	C	`conf`	Improving Residue-Level Sparsity in RNS-based Neural Network Hardware Accelerators via Regularization. ARITH Emmanouil Kavvousanos, Vasilis Sakellariou, Ioannis Kouretas, Vassilis Paliouras, Thanos Stouraitis
2023	A	`conf`	Invited Paper: Dilithium Hardware-Accelerated Application Using OpenCL-Based High-Level Synthesis. ICCAD Alexander El-Kady, Apostolos P. Fournaris, Vassilis Paliouras
2023	—	`conf`	Modified Logarithmic Multiplication Approximation for Machine Learning. AICAS Ioannis Kouretas, Vassilis Paliouras, Thanos Stouraitis
2023	J	`jnl`	Noise-Shaping Binary-to-Stochastic Converters for Reduced-Length Bit-Streams. IEEE Trans. Emerg. Top. Comput. Kleanthis Papachatzopoulos, Vassilis Paliouras
2023	J	`jnl`	Path-Based Delay Variation Models for Parallel-Prefix Adders. IEEE Trans. Emerg. Top. Comput. Kleanthis Papachatzopoulos, Vassilis Paliouras
2023	Misc	`conf`	Received Power Maximization with Practical Phase-Dependent Amplitude Response in RIS-Aided OFDM Wireless Communications. ICASSP Dimitris Kompostiotis, Dimitris Vordonis, Vassilis Paliouras
2023	—	`conf`	Secrecy Rate Maximization in RIS-Enabled OFDM Wireless Communications: The Circuit-Based Reflection Model Case. ICC Workshops Dimitris Kompostiotis, Dimitris Vordonis, Vassilis Paliouras, George C. Alexandropoulos
2022	C	`conf`	A High-performance RNS LSTM block. ISCAS Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas, Hani Saleh, Thanos Stouraitis
2022	—	`conf`	A Low-Latency Syndrome-based Deep Learning Decoder Architecture and its FPGA Implementation. MOCAST Emmanouil Kavvousanos, Vassilis Paliouras
2022	—	`conf`	Hardware Aspects of Iterative Receivers for V2X Applications. MOCAST Thodoris Spanos, Vassilis Paliouras
2022	C	`conf`	High-Level Synthesis design approach for Number-Theoretic Multiplier. VLSI-SoC Alexander El-Kady, Apostolos P. Fournaris, Evangelos Haleplidis, Vassilis Paliouras
2022	—	`conf`	Reconfigurable Intelligent Surface-Aided OFDM Wireless Communications: Hardware Aspects of Reflection Optimization Methods. MOCAST Dimitris Vordonis, Dimitris Kompostiotis, Vassilis Paliouras
2022	C	`conf`	Sensitivity to Threshold Voltage Variations of Exact and Incomplete Prefix Addition Trees. ISCAS Kleanthis Papachatzopoulos, Vassilis Paliouras
2021	—	`conf`	A 5G-code based iterative Non-Binary LDPC decoder. ICECS Dimitris Chytas, Vassilis Paliouras
2021	J	`jnl`	A Multirate Fully Parallel LDPC Encoder for the IEEE 802.11n/ac/ax QC-LDPC Codes Based on Reduced Complexity XOR Trees. IEEE Trans. Very Large Scale Integr. Syst. Ahmed Mahdi, Nikos Kanistras, Vassilis Paliouras
2021	C	`conf`	A Novel Stochastic Polar Architecture for All-Digital Transmission. ISCAS Chris Andriakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras
2021	C	`conf`	An FPGA Accelerator for Spiking Neural Network Simulation and Training. ISCAS Vasilis Sakellariou, Vassilis Paliouras
2021	—	`conf`	Hardware Aspects of Parallel Neural Network Implementation. MOCAST Ioannis Kouretas, Vassilis Paliouras
2021	J	`jnl`	Hardware Implementation and Performance Analysis of Improved Sphere Decoder in Spatially Correlated Massive MIMO Channels. IEEE Open J. Commun. Soc. Dimitris Vordonis, Vassilis Paliouras
2021	C	`conf`	High-Level Synthesis design approach for Number-Theoretic Transform Implementations. VLSI-SoC Alexander El-Kady, Apostolos P. Fournaris, Thanasis Tsakoulis, Evangelos Haleplidis, Vassilis Paliouras
2021	—	`conf`	On Reducing the Number of Multiplications in RNS-based CNN Accelerators. ICECS Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas, Hani Saleh, Thanos Stouraitis
2021	B	`conf`	Optimizing Deep Learning Decoders for FPGA Implementation. FPL Emmanouil Kavvousanos, Vassilis Paliouras
2021	C	`conf`	Simplified Hardware Implementation of Memoryless Dot Product for Neural Network Inference. ISCAS Ioannis Kouretas, Vassilis Paliouras
2021	C	`conf`	Sum Propagate Adders. ARITH Giorgos Dimitrakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras
2021	J	`jnl`	Sum Propagate Adders. IEEE Trans. Emerg. Top. Comput. Giorgos Dimitrakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras
2020	—	`conf`	An Iterative Approach to Syndrome-based Deep Learning Decoding. GLOBECOM (Workshops) Emmanouil Kavvousanos, Vassilis Paliouras
2020	—	`conf`	Approximate Sorting Check Node Processing in Non-Binary LDPC Decoders. ICECS Dimitris Chytas, Vassilis Paliouras
2020	J	`jnl`	Implementing the Residue Logarithmic Number System Using Interpolation and Cotransformation. IEEE Trans. Computers Mark G. Arnold, Vassilis Paliouras, Ioannis Kouretas
2020	C	`conf`	Maximum Delay Models for Parallel-Prefix Adders in the Presence of Threshold Voltage Variations. ARITH Kleanthis Papachatzopoulos, Vassilis Paliouras
2020	C	`conf`	Novel Noise-Shaping Stochastic-Computing Converters for Digital Filtering. ISCAS Kleanthis Papachatzopoulos, Chris Andriakopoulos, Vassilis Paliouras
2019	—	`conf`	Hardware Implementation Aspects of a Syndrome-based Neural Network Decoder for BCH Codes. NORCAS Emmanouil Kavvousanos, Vassilis Paliouras
2019	—	`conf`	One-Hot Residue Logarithmic Number Systems. PATMOS Mark G. Arnold, Ioannis Kouretas, Vassilis Paliouras, Austin Morgan
2019	—	`conf`	Radix-3 low-complexity modulo-M multipliers. PATMOS Ioannis Kouretas, Vassilis Paliouras
2019	—	`conf`	Simplified Hardware Implementation of the Softmax Activation Function. MOCAST Ioannis Kouretas, Vassilis Paliouras
2019	—	`conf`	Sphere Decoder for Massive MIMO Systems. NORCAS Dimitris Vordonis, Vassilis Paliouras
2019	J	`jnl`	Static Delay Variation Models for Ripple-Carry and Borrow-Save Adders. IEEE Trans. Circuits Syst. I Regul. Pap. Kleanthis Papachatzopoulos, Vassilis Paliouras
2019	C	`conf`	Under- and Overflow Detection in the Residue Logarithmic Number System. ARITH Mark G. Arnold, Ioannis Kouretas, Vassilis Paliouras, John R. Cowles
2019	—	`conf`	Versatile Hardware Generation of alpha-Stable Noise for PLC Channel Emulation. ICECS Konstantina Karagianni, Vassilis Paliouras
2018	J	`jnl`	A Reconfigurable LDPC Decoder Optimized for 802.11n/ac Applications. IEEE Trans. Very Large Scale Integr. Syst. Ioannis Tsatsaragkos, Vassilis Paliouras
2018	—	`conf`	A novel algorithm and hardware architecture for low-complexity soft demappers. MOCAST Andreas Kalampoukas, Vassilis Paliouras
2018	—	`conf`	Data representation and hardware aspects in a fully-folded successive-cancellation polar decoder. MOCAST Christos Andriakopoulos, Vassilis Paliouras
2018	—	`conf`	Hardware aspects of Long Short Term Memory. ICECS Ioannis Kouretas, Vassilis Paliouras
2018	—	`conf`	Logarithmic number system for deep learning. MOCAST Ioannis Kouretas, Vassilis Paliouras
2018	J	`jnl`	Low-Power Addition With Borrow-Save Adders Under Threshold Voltage Variability. IEEE Trans. Circuits Syst. II Express Briefs Kleanthis Papachatzopoulos, Vassilis Paliouras
2018	—	`conf`	Low-cost soft-error compensation for transposed FIR digital filters. MOCAST Vassilis Paliouras, Konstantina Karagianni, Yann Oster
2018	—	`conf`	Quantitative Evaluation of Certain SET Mitigation Techniques for Multiply-Accumulate Circuits and State Machines. PATMOS Vassilis Paliouras, Konstantina Karagianni, Yann Oster
2018	J	`jnl`	Reconfigurable RO-Path Delay Sensor. IEEE Trans. Circuits Syst. II Express Briefs Panagiotis Sakellariou, Vassilis Paliouras
2018	—	`conf`	Simplified Deep-Learning-based decoders for linear block codes. ICECS Emmanouil Kavvousanos, Vassilis Paliouras, Ioannis Kouretas
2017	—	`conf`	An approximate hardware check node for λ-min-based LDPC decoders. EUSIPCO Georgios Perris-Samios, Vassilis Paliouras
2017	—	`conf`	Hardware trade-offs for massive MIMO uplink detection based on Newton iteration method. MOCAST Alexios Thanos, Vassilis Paliouras
2017	C	`conf`	Logarithmic number system addition-subtraction using fractional normalization. ISCAS Giorgos Tsiaras, Vassilis Paliouras
2017	—	`conf`	Multi-operand logarithmic addition/subtraction based on Fractional Normalization. MOCAST Giorgos Tsiaras, Vassilis Paliouras
2017	C	`conf`	Work in progress: An introduction to computing course using a Python-based experiential approach. EDUCON Nikolaos M. Avouris, Kyriakos N. Sgarbas, Vassilis Paliouras, Michalis Koukias
2016	J	`jnl`	Application-Specific Low-Power Multipliers. IEEE Trans. Computers Panagiotis Sakellariou, Vassilis Paliouras
2016	C	`conf`	Dynamic delay variation behaviour of RNS multiply-add architectures. ISCAS Kleanthis Papachatzopoulos, Ioannis Kouretas, Vassilis Paliouras
2015	J	`jnl`	Approximate Algorithms for Identifying Minima on Min-Sum LDPC Decoders and Their Hardware Implementation. IEEE Trans. Circuits Syst. II Express Briefs Ioannis Tsatsaragkos, Vassilis Paliouras
2015	J	`jnl`	On the Encoding Complexity of Quasi-Cyclic LDPC Codes. IEEE Trans. Signal Process. Ahmed Mahdi, Vassilis Paliouras
2014	J	`jnl`	A Low Complexity-High Throughput QC-LDPC Encoder. IEEE Trans. Signal Process. Ahmed Mahdi, Vassilis Paliouras
2014	—	`conf`	A technique for the identification of trapping sets in LDPC codes. ICECS Christos Vasilopoulos, Vassilis Paliouras
2014	—	`conf`	Effective sum of squares implementation for BPSK soft-decision decoding. ICECS P. Mermigkas, Vassilis Paliouras
2013	—	`conf`	A semi-analytical bivariate Gaussian model of the approximation error impact on the Min-Sum LDPC decoding algorithm. SiPS Nikos Kanistras, Vassilis Paliouras
2013	C	`conf`	Delay-variation-tolerant FIR filter architectures based on the Residue Number System. ISCAS Ioannis Kouretas, Vassilis Paliouras
2013	J	`jnl`	Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters. IEEE Trans. Computers Ioannis Kouretas, Charalambos Basetas, Vassilis Paliouras
2012	—	`conf`	An FPGA-based prototyping method for verification, characterization and optimization of LDPC error correction systems. ICSAMOS Panagiotis Sakellariou, Ioannis Tsatsaragkos, Nikos Kanistras, Ahmed Mahdi, Vassilis Paliouras
2012	—	`conf`	Error Floor Compensation for LDPC Codes Using Concatenated Schemes. SiPS G. Spourlis, Ioannis Tsatsaragkos, Nikos Kanistras, Vassilis Paliouras
2012	—	`conf`	Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAs. ICECS Ahmed Mahdi, Panagiotis Sakellariou, Nikos Kanistras, Ioannis Tsatsaragkos, Vassilis Paliouras
2012	—	`conf`	Low-Power Delay Sensors on FPGAs. PATMOS Panagiotis Sakellariou, Vassilis Paliouras
2012	—	`conf`	Low-power two's-complement multiplication based on selective activation. ICECS Panagiotis Sakellariou, Vassilis Paliouras
2012	—	`conf`	Propagation of LLR Saturation and Quantization Error in LDPC Min-Sum Iterative Decoding. SiPS Nikos Kanistras, Ioannis Tsatsaragkos, Vassilis Paliouras
2012	C	`conf`	Residue arithmetic for designing multiply-add units in the presence of non-gaussian variation. ISCAS Ioannis Kouretas, Vassilis Paliouras
2012	—	`conf`	Simplified Multi-Level Quasi-Cyclic LDPC Codes for Low-Complexity Encoders. SiPS Ahmed Mahdi, Vassilis Paliouras
2011	—	`conf`	A Residue Logarithmic Number System ALU using interpolation and cotransformation. ASAP Mark G. Arnold, Ioannis Kouretas, Vassilis Paliouras
2011	Misc	`conf`	A flexible high-throughput hardware architecture for a gaussian noise generator. ICASSP Ioannis Paraskevakos, Vassilis Paliouras
2011	—	`conf`	A flexible layered LDPC decoder. ISWCS Ioannis Tsatsaragkos, Vassilis Paliouras
2011	—	`conf`	A syndrome-based LDPC decoder with very low error floor. DSP Ioannis Tsatsaragkos, Nikos Kanistras, Vassilis Paliouras
2011	—	`conf`	An encoding scheme and encoder architecture for rate-compatible QC-LDPC codes. SiPS Ahmed Mahdi, Nikos Kanistras, Vassilis Paliouras
2011	—	`conf`	Digital baseband challenges for a 60GHz gigabit link. ICECS Nikos Kanistras, Ioannis Tsatsaragkos, Ahmed Mahdi, Konstantina Karagianni, Vassilis Paliouras, Fotios Gioulekas, E. Lalos, Kostas Adaos, Michael K. Birbas, Panos Karaivazoglou, M. V. Koziotis, M. Perakis
2011	J	`jnl`	Impact of Approximation Error on the Decisions of LDPC Decoding. J. Signal Process. Syst. Nikos Kanistras, Vassilis Paliouras
2011	—	`conf`	Multiple LDPC decoder of very low bit-error rate. DSP Ioannis Tsatsaragkos, Nikos Kanistras, Vassilis Paliouras
2011	—	`conf`	Next generation millimeter wave backhaul radio: Overall system design for GbE 60GHz PtP wireless radio of high CMOS integration. ICECS Rodoula Makri, Petros Tsenes, Dimitrios Economou, Yannis Papananos, Dimitrios Dervenis, Michael K. Birbas, John C. Kikidis, Vassilis Paliouras, Grigorios Kalivas, Alexios N. Birbas, Panos Karaivazoglou, Yorgos Stratakos, John Korinthios, Stelios Siskos, Alkis A. Hatzopoulos, John Komninos, Serafeim Katsikas, Konstantinos N. Voudouris, Andreas Rigas, George Agapiou, Polivios Raxis
2011	—	`conf`	On the impact of encoding on the complexity of residue arithmetic circuits. ICECS E. Theodorakis, Vassilis Paliouras
2011	C	`conf`	Towards a Quaternion Complex Logarithmic Number System. IEEE Symposium on Computer Arithmetic Mark G. Arnold, John R. Cowles, Vassilis Paliouras, Ioannis Kouretas
2011	—	`conf`	Using the arithmetic representation properties of data to reduce the area and power consumption of FFT circuits for wireless OFDM systems. SiPS Andreas Brokalakis, Vassilis Paliouras
2010	—	`conf`	RNS multi-voltage low-power multiply-add unit. ICECS Ioannis Kouretas, Vassilis Paliouras
2010	—	`conf`	Residue Arithmetic for Designing Low-Power Multiply-Add Units. PATMOS Ioannis Kouretas, Vassilis Paliouras
2010	C	`conf`	Residue arithmetic bases for reducing delay variation. ISCAS Ioannis Kouretas, Vassilis Paliouras
2010	—	`conf`	VLSI implementation and performance of turbo decoding stopping criteria. ICECS Angelos Spanos, Vassilis Paliouras
2009	J	`jnl`	A Low-Complexity High-Radix RNS Multiplier. IEEE Trans. Circuits Syst. I Regul. Pap. Ioannis Kouretas, Vassilis Paliouras
2009	J	`jnl`	A Low-Complexity PTS-based PAPR Reduction Technique for OFDM Signals without Transmission of Side Information. J. Signal Process. Syst. Theodoros Giannopoulos, Vassilis Paliouras
2009	—	`conf`	High-radix residue arithmetic bases for low-power DSP systems. DPS Ioannis Kouretas, Vassilis Paliouras
2009	—	`conf`	Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units. PATMOS Ioannis Kouretas, Vassilis Paliouras
2009	C	`conf`	Variation-tolerant Design Using Residue Number System. DSD Ioannis Kouretas, Vassilis Paliouras
2008	—	`conf`	A frequency-domain interpolation implementation for OFDM transmitters. ISWPC Eleni Fotopoulou, Vassilis Paliouras, Thanos Stouraitis
2008	—	`conf`	Impact of roundoff error on the decisions of the Log Sum-Product algorithm for LDPC decoding. SiPS Nikos Kanistras, Vassilis Paliouras
2008	—	`conf`	Impact of roundoff errors in LDPC decoding. ISWPC Nikos Kanistras, Vassilis Paliouras
2008	C	`conf`	Low-power logarithmic number system addition/subtraction and their impact on digital filters. ISCAS Ioannis Kouretas, Charalambos Basetas, Vassilis Paliouras
2008	—	`conf`	Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication. PATMOS Ioannis Kouretas, Vassilis Paliouras
2008	—	`conf`	On the implementation of bus-based architectures for LDPC decoding. ISWPC G. Aggouras, Vassilis Paliouras
2008	—	`conf`	Packet detector for multiband UWB. ISWPC D. Pettas, Vassilis Paliouras
2008	—	`conf`	Relationship among BER, power consumption and PAPR. ISWPC Theodoros Giannopoulos, Vassilis Paliouras
2008	—	`conf`	Roundoff error effects on a Quasi-Newton frequency domain channel equalizer. ISWPC Panos Karaivazoglou, Konstantina Karagianni, Vassilis Paliouras, Kostas Berberidis
2007	—	`conf`	Low-Power Digital Filtering Based on the Logarithmic Number System. PATMOS Charalambos Basetas, Ioannis Kouretas, Vassilis Paliouras
2007	—	`conf`	On The Complexity of Joint Demodulation and Convolutional Decoding. SiPS Dimitris Gkrimpas, Vassilis Paliouras
2006	—	`conf`	A Low-Complexity PTS-based PAPR Reduction Technique for OFDM Signals without Transmission of Side Information. SiPS Theodoros Giannopoulos, Vassilis Paliouras
2006	C	`conf`	A novel technique for low-power D/A conversion based on PAPR reduction. ISCAS Theodoros Giannopoulos, Vassilis Paliouras
2006	J	`jnl`	Editorial. J. Low Power Electron. Johan Vounckx, Vassilis Paliouras
2006	—	`conf`	Low-Power Maximum Magnitude Computation for PAPR Reduction in OFDM Transmitters. PATMOS Theodoros Giannopoulos, Vassilis Paliouras
2006	—	`conf`	Low-Power Saturated Arithmetic and its Application in VLSI Architectures for OFDM Modems. SiPS Konstantina Karagianni, Vassilis Paliouras, Theodoros Giannopoulos
2006	—	`conf`	Novel efficient weighting factors for PTS-based PAPR reduction in low-power OFDM transmitters. EUSIPCO Theodoros Giannopoulos, Vassilis Paliouras
2006	—	`conf`	Simplified Criteria for Early Iterative Decoding Termination. SiPS Spyros Gidaros, Vassilis Paliouras
2005	—	`ed.`	Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings PATMOS Vassilis Paliouras, Johan Vounckx, Diederik Verkest
2005	—	`conf`	Low-Power Aspects of Nonlinear Signal Processing. PATMOS Konstantina Karagianni, Vassilis Paliouras
2005	—	`conf`	Low-Power VLSI Architectures for OFDM Transmitters Based on PAPR Reduction. PATMOS Theodoros Giannopoulos, Vassilis Paliouras
2005	—	`conf`	Using CLNS for FFTs in OFDM demodulation of UWB receivers. ISCAS (4) Panagiotis D. Vouzis, Mark G. Arnold, Vassilis Paliouras
2004	J	`jnl`	A novel architecture and a systematic graph-based optimization methodology for modulo multiplication. IEEE Trans. Circuits Syst. I Regul. Pap. Giorgos Dimitrakopoulos, Vassilis Paliouras
2004	—	`conf`	An efficient architecture for peak-to-average power ratio reduction in OFDM systems in the presence of pulse-shaping filtering. ISCAS (4) Theodoros Giannopoulos, Vassilis Paliouras
2004	B	`conf`	An efficient computational method and a VLSI architecture for digital filtering of CP-OFDM signals. GLOBECOM Eleni Fotopoulou, Vassilis Paliouras
2004	—	`conf`	An efficient memory compression scheme for 8 k FFT in a DVB-T receiver and the corresponding error model. ISCAS (4) Stamatis Krommydas, Vassilis Paliouras
2004	—	`ed.`	Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings PATMOS Enrico Macii, Odysseas G. Koufopavlou, Vassilis Paliouras
2004	—	`conf`	Optimal Logarithmic Representation in Terms of SNR Behavior. PATMOS Panagiotis D. Vouzis, Vassilis Paliouras
2003	—	`conf`	A computational technique and a VLSI architecture for digital pulse shaping in OFDM modems. ISCAS (2) Eleni Fotopoulou, Vassilis Paliouras, Thanos Stouraitis
2003	—	`conf`	High-radix redundant circuits for RNS modulo r ISCAS (5) Ioannis Kouretas, Vassilis Paliouras
2002	—	`conf`	High-radix modulo r ICECS Ioannis Kouretas, Vassilis Paliouras
2002	—	`conf`	Multi-voltage low power convolvers using the polynomial residue number system. ACM Great Lakes Symposium on VLSI Vassilis Paliouras, Alexander Skavantzos, Thanos Stouraitis
2001	C	`conf`	Low-Power Properties of the Logarithmic Number System. IEEE Symposium on Computer Arithmetic Vassilis Paliouras, Thanos Stouraitis
2001	J	`jnl`	Operation-Saving VLSI Architectures for 3D Geometrical Transformations. IEEE Trans. Computers Konstantina Karagianni, Vassilis Paliouras, George Diamantakos, Thanos Stouraitis
2001	—	`conf`	Signal activity and power consumption reduction using the logarithmic number system. ISCAS (2) Vassilis Paliouras, Thanos Stouraitis
2001	—	`conf`	VLSI architectures for blind equalization based on fractional-order statistics. ICECS Vassilis Paliouras, J. Dagres, Panagiotis Tsakalides, Thanos Stouraitis
2000	—	`conf`	High-radix residue number system forward and inverse converters. ICECS Vassilis Paliouras, Thanos Stouraitis
2000	—	`conf`	Logarithmic Number System for Low-Power Arithmetic. PATMOS Vassilis Paliouras, Thanos Stouraitis
1999	—	`conf`	Novel high-radix residue number system multipliers and adders. ISCAS (1) Vassilis Paliouras, Thanos Stouraitis
1998	—	`conf`	A VLSI architecture for fast and accurate floating-point sine/cosine evaluation. ICECS Vassilis Paliouras, Konstantina Karagianni, Thanos Stouraitis
1998	—	`conf`	A very-long instruction word digital signal processor based on the logarithmic number system. ICECS Vassilis Paliouras, J. Karagiannis, G. Aggouras, Thanos Stouraitis
1997	Misc	`conf`	An operation-saving VLSI geometry engine core. ICASSP Konstantina Karagianni, George Diamantakos, Vassilis Paliouras, Thanos Stouraitis
1997	—	`conf`	Area-time performance of VLSI FIR filter architectures based on residue arithmetic. EUROMICRO Vassilis Paliouras, Thanos Stouraitis
1996	—	`conf`	Efficient algorithms and VLSI architectures for trigonometric functions in the logarithmic number system based on the subtraction function. ICECS E. N. Malamas, Vassilis Paliouras, Thanos Stouraitis
1995	C	`conf`	A Novel Algorithm for Multi-Operand Logarithmic Number System Addition and Subtraction Using Polynominal Approximation. ISCAS I. Orginos, Vassilis Paliouras, Thanos Stouraitis
1994	C	`conf`	Systematic Design of Multi-Modulus/Multi-Function Residue Number System Processors. ISCAS Vassilis Paliouras, Thanos Stouraitis
1993	C	`conf`	Methodology for the Design of Signed-digit DSP Processors. ISCAS Vassilis Paliouras, Dimitrios Soudris, Thanos Stouraitis
1993	—	`conf`	Systematic design of full adder-based architectures for convolution. ICASSP (1) Dimitrios Soudris, Vassilis Paliouras, Thanos Stouraitis, Alexander Skavantzos, Constantinos E. Goutis
1992	Misc	`conf`	Systematic development of architectures for multidimensional DSP using the residue number system. ICASSP Dimitrios Soudris, Vassilis Paliouras, Thanos Stouraitis