Vassilios A. Chouliaras

48 papers B 5Journal 18Unranked 24

Year	Rank	Type	Title / Venue / Authors
2018	—	`conf`	Development of Sensorised Resistance Band for Objective Exercise Measurement: Activities Classification Trial. EMBC Jianjia Ma, Eef Hogervorst, Daniele Magistro, Vassilios A. Chouliaras, Massimiliano Zecca
2017	—	`conf`	Shape reconstruction using instruction systolic array. IEEE SENSORS Partheepan Kandaswamy, James A. Flint, Vassilios A. Chouliaras
2016	J	`jnl`	An OpenCL software compilation framework targeting an SoC-FPGA VLIW chip multiprocessor. J. Syst. Archit. Samuel J. Parker, Vassilios A. Chouliaras
2016	J	`jnl`	An efficient multiple precision floating-point Multiply-Add Fused unit. Microelectron. J. Konstantinos Manolopoulos, Dionisios I. Reisis, Vassilios A. Chouliaras
2016	J	`jnl`	VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads. Microprocess. Microsystems Vassilios A. Chouliaras, David Stevens, Vincent M. Dwyer
2013	J	`jnl`	Architecture, performance modeling and VLSI implementation methodologies for ASIC vector processors: A case study in telephony workloads. Microprocess. Microsystems Vassilios A. Chouliaras, Konstantia Koutsomyti, Simon Parr, David J. Mulvaney, Mark Milward
2013	—	`conf`	Autonomous learning design in system-on-chip. ROBIO Yimin Zhou, Ludovic A. Krundel, David J. Mulvaney, Vassilios A. Chouliaras, Guoqing Xu, Guoqiang Fu
2013	J	`jnl`	Bidirectional electromigration failure. Microelectron. Reliab. M. K. Lim, Vassilios A. Chouliaras, Chee Lip Gan, Vincent M. Dwyer
2012	J	`jnl`	BioThreads: A Novel VLIW-Based Chip Multiprocessor for Accelerating Biomedical Image Processing Applications. IEEE Trans. Biomed. Circuits Syst. David Stevens, Vassilios A. Chouliaras, Vicente Azorin-Peris, Jia Zheng, Angelos Echiadis, Sijung Hu
2012	—	`conf`	Embedded UML design flow to the configurable LE1 MultiCore VLIW processor. ReCoSoC Mark Milward, David Stevens, Vassilios A. Chouliaras
2011	—	`conf`	An efficient multiple precision floating-point multiplier. ICECS Konstantinos Manolopoulos, Dionisios I. Reisis, Vassilios A. Chouliaras
2011	—	`conf`	Customizing a VLIW Chip Multiprocessor for Motion Estimation Algorithms. ARCS Workshops Vassilios A. Chouliaras, George Lentaris, Dionisios I. Reisis, David Stevens
2010	—	`conf`	An efficient dual-mode floating-point Multiply-Add Fused Unit. ICECS Konstantinos Manolopoulos, Dionysios I. Reisis, Vassilios A. Chouliaras
2010	—	`conf`	Autonomous Design in VLSI: An In-House Universal Cellular Neural Platform. ISVLSI Ludovic A. Krundel, David J. Mulvaney, Vassilios A. Chouliaras
2010	—	`conf`	Autonomous Design in VLSI: Growing and Learning on Silicon. ISVLSI Ludovic A. Krundel, David J. Mulvaney, Vassilios A. Chouliaras
2010	J	`jnl`	Fully Systolic FFT Architecture for Giga-sample Applications. J. Signal Process. Syst. Konstantinos Babionitakis, Vassilios A. Chouliaras, Konstantinos Manolopoulos, Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos
2010	—	`conf`	LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support. ISVLSI David Stevens, Vassilios A. Chouliaras
2009	—	`conf`	A configurable length, Fused Multiply-Add floating point unit for a VLIW processor. SoCC Vassilios A. Chouliaras, Konstantinos Manolopoulos, Dionysios I. Reisis
2009	—	`conf`	Efficient cascaded VLSI FFT architecture for OFDM systems. ICECS Vassilios A. Chouliaras, Panagiotis Galiatsatos, Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos
2009	—	`conf`	Evaluating the performance of a configurable, extensible VLIW processor in FFT execution. ICECS David Stevens, Nick Glynn, Panagiotis Galiatsatos, Vassilios A. Chouliaras, Dionysios I. Reisis
2008	J	`jnl`	A Novel Delta Sigma Control System Processor and Its VLSI Implementation. IEEE Trans. Very Large Scale Integr. Syst. Xiaofeng Wu, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger M. Goodall
2008	B	`conf`	A configurable and programmable motion estimation processor for the H.264 video codec. FPL José Luis Núñez-Yáñez, Eddie Hung, Vassilios A. Chouliaras
2008	J	`jnl`	Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study. Integr. Vassilios A. Chouliaras, Vincent M. Dwyer, Shahrukh Agha, José L. Núñez-Yáñez, Dionysios I. Reisis, Konstantinos Nakos, Konstantinos Manolopoulos
2008	—	`conf`	Feasibility of Imaging Photoplethysmography. BMEI (2) Jia Zheng, Sijung Hu, Vassilios A. Chouliaras, Ron Summers
2007	—	`conf`	A Transmission Line Modelling VLSI processor designed with a novel Electronic System Level Methodology. ICECS Vassilios A. Chouliaras, James A. Flint, Yibin Li
2007	B	`conf`	Dynamic Voltage Scaling in a FPGA-based System-on-Chip. FPL José L. Núñez-Yáñez, Vassilios A. Chouliaras, Jiri Gaisler
2007	J	`jnl`	Hardware implementation of a novel genetic algorithm. Neurocomputing Zhenhuan Zhu, David J. Mulvaney, Vassilios A. Chouliaras
2007	—	`conf`	High Performance 16K, 64K, 256K complex points VLSI Systolic FFT Architectures. ICECS Konstantinos Manolopoulos, Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos, Vassilios A. Chouliaras
2007	J	`jnl`	Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor. IEEE Trans. Computers Emmanuel Touloupis, James A. Flint, Vassilios A. Chouliaras, David D. Ward
2006	—	`conf`	A High Performance VLSI FFT Architecture. ICECS Konstantinos Babionitakis, Konstantinos Manolopoulos, Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos, Vassilios A. Chouliaras
2006	—	`conf`	A Novel Processor Architecture for Real-Time Control. Asia-Pacific Computer Systems Architecture Conference Xiaofeng Wu, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger Goodall, Tanya Vladimirova
2006	J	`jnl`	Hardware assisted rate distortion optimization with embedded CABAC accelerator for the H.264 advanced video codec. IEEE Trans. Consumer Electron. José L. Núñez-Yáñez, Vassilios A. Chouliaras, Daniele Alfonso, Fabrizio S. Rovati
2006	B	`conf`	Investigation Of A New Genetic Algorithm Designed For System-On-Chip Realization. IEEE Congress on Evolutionary Computation Zhenhuan Zhu, David J. Mulvaney, Vassilios A. Chouliaras
2006	—	`conf`	SystemC-defined SIMD instructions for high performance SoC architectures. ICECS Vassilios A. Chouliaras, Konstantia Koutsomyti, Tom R. Jacobs, Simon Parr, David J. Mulvaney, Robert Thomson
2006	J	`jnl`	Thread-parallel MPEG-2, MPEG-4 and H.264 video encoders for SoC multi-processor architectures. IEEE Trans. Consumer Electron. Tom R. Jacobs, Vassilios A. Chouliaras, David J. Mulvaney
2005	J	`jnl`	A Configurable Statistical Lossless Compression Core Based on Variable Order Markov Modeling and Arithmetic Coding. IEEE Trans. Computers José L. Núñez-Yáñez, Vassilios A. Chouliaras
2005	J	`jnl`	A multi-standard video accelerator based on a vector architecture. IEEE Trans. Consumer Electron. Vassilios A. Chouliaras, José L. Núñez-Yáñez, David J. Mulvaney, Fabrizio S. Rovati, Daniele Alfonso
2005	—	`conf`	Applying data-parallel and scalar optimizations for the efficient implementation of the G.729A and G.723.1 speech coding standards. SIP Konstantia Koutsomyti, S. R. Parr, Vassilios A. Chouliaras, José L. Núñez-Yáñez
2005	—	`conf`	Configurable Multiprocessors for High-Performance MPEG-4 Video Coding. ISVLSI Vassilios A. Chouliaras, Tom R. Jacobs, Ashwin K. Kumaraswamy, José L. Núñez-Yáñez
2005	—	`conf`	Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec. ASAP José L. Núñez-Yáñez, Vassilios A. Chouliaras
2005	J	`jnl`	High-performance arithmetic coding VLSI macro for the H264 video compression standard. IEEE Trans. Consumer Electron. José L. Núñez-Yáñez, Vassilios A. Chouliaras
2005	B	`conf`	On the Performance Improvement of Sub-sampling MPEG-2 Motion Estimation Algorithms with Vector/SIMD Architectures. ACIVS Vassilios A. Chouliaras, Vincent M. Dwyer, Shahrukh Agha
2005	—	`—`	Parallelism and the software-hardware interface in embedded systems. Vassilios A. Chouliaras
2005	B	`conf`	Reduced-Bit, Full Search Block-Matching Algorithms and Their Hardware Realizations. ACIVS Vincent M. Dwyer, Shahrukh Agha, Vassilios A. Chouliaras
2004	—	`conf`	An application-specific processor hard macro for real-time control. SoCC Xiaofeng Wu, Vassilios A. Chouliaras, Roger Goodall
2004	J	`jnl`	Three novel low complexity scanning orders for MPEG-2 full search motion estimation. Real Time Imaging Christos Grecos, Azilah Saparon, Vassilios A. Chouliaras
2003	—	`conf`	A code compression scheme for improving SoC performance. SoC E. G. Nikolova, David J. Mulvaney, Vassilios A. Chouliaras, José L. Núñez-Yáñez
2003	J	`jnl`	Scalar coprocessors for accelerating the G723.1 and G729A speech coders. IEEE Trans. Consumer Electron. Vassilios A. Chouliaras, José L. Núñez-Yáñez