Vasantha M. H.

14 papers C 2Misc 3Journal 1Unranked 8

Year	Rank	Type	Title / Venue / Authors
2026	Misc	`conf`	A Robust CMOS Schmitt Trigger Architecture with Improved Noise Immunity and Hysteresis Control. VLSID Siddharth R. K., Shasidhar Reddy, Cheni Deepankar, Karteek Dokala, Vasantha M. H., Nithin Kumar Y. B.
2026	Misc	`conf`	Partial Product Grouping-Based Approximate Multipliers for Deep Learning Inference. VLSID Boggu Priestly Samarpana, Siddharth R. K., Geeta Shet, Nithin Kumar Y. B., Vasantha M. H.
2025	C	`conf`	A 0.9 V Configurable Dual Mode Comparator using a Supply Boosting Technique. ISCAS Sourabh Mestry, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Edoardo Bonizzoni
2024	—	`conf`	Power Reduction of a Level Triggered D Flip-Flop using Clock Gating and Power Gating Techniques. iSES Yamana Ashok Kumar, Nithin Kumar Y. B., Vasantha M. H., Siddharth R. K.
2024	—	`conf`	Side Channel Attack on 8051 Microcontroller. iSES Manda Yuktha, Pragati Patel, Vasantha M. H.
2023	Misc	`conf`	A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process. VLSID Rupesh D. Kadhao, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Devesh Dwivedi
2023	—	`conf`	Approximate Three-Operand Binary Adder for Error-Resilient Applications. iSES Darshan Halliyavar, Siddharth R. K., Vasantha M. H., Nithin Kumar Y. B., Sithara Raveendran
2021	C	`conf`	A 1-V, 5-Bit, 180-µW, Differential Pulse Position Modulation ADC in 65-nm CMOS Process. ISCAS Peta Guruprakashkumar, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Edoardo Bonizzoni
2020	—	`conf`	A 1.8 V, Mode-Configurable Hybrid Smart ADC. iSES Tejas J. Shahane, Siddharth R. K., Kumar Y. B. Nithin, Vasantha M. H.
2020	—	`conf`	A Novel Single Event Upset Tolerant 12T Memory Cell for Aerospace Applications. ISVLSI Suraj Dohar, Siddharth R. K., Vasantha M. H., Nithin Kumar Y. B.
2020	—	`conf`	A Wideband 12 Phase Ring Oscillator for 5G Applications. MWSCAS Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Nithin Kumar Y. B., Vasantha M. H., Ramnath Kini
2020	J	`jnl`	IET Circuits, Devices & Systems. IET Circuits Devices Syst. Vivek Sharma, Nithin Kumar Y. B., Vasantha M. H.
2019	—	`conf`	Design and Analysis of Energy Efficient Reversible Logic based Full Adder. MWSCAS Jagadeesh Pujar, Sithara Raveendran, Trilochan Panigrahi, Vasantha M. H., Nithin Kumar Y. B.
2012	—	`conf`	0.5 V, Low Power, 1 MHz Low Pass Filter in 0.18 µm CMOS Process. ISED Vasantha M. H., Tonse Laxminidhi