Vasant B. Rao

21 papers A* 4A 2Misc 1Journal 10Unranked 3
YearRankTypeTitle / Venue / Authors
2011 J jnl
Design methodology for the IBM POWER7 microprocessor.
IBM J. Res. Dev.
Joshua Friedrich, Ruchir Puri, Uwe Brandt, Markus Bühler, Jack DiLullo, Jeremy Hopkins, Mozammel Hossain, Michael A. Kazda, Joachim Keinert, Zahi M. Kurzum, Douglass Lamb, Alice Lee, Frank Musante, Jens Noack, Peter J. Osler, Stephen D. Posluszny, Haifeng Qian, Shyam Ramji, Vasant B. Rao, Lakshmi N. Reddy, Haoxing Ren, Thomas E. Rosser, Benjamin R. Russell, Cliff C. N. Sze, Gustavo E. Téllez
2002 — conf
Aggressive crunching of extracted RC netlists.
Timing Issues in the Specification and Synthesis of Digital Systems
Vasant B. Rao, Jeffrey Soreff, Ravichander Ledalla, Fred L. Yang
1996 J jnl
Design planning for high-performance ASICs.
IBM J. Res. Dev.
John Y. Sayah, Rajesh Gupta, Deepak D. Sherlekar, Philip S. Honsinger, Jitendra M. Apte, S. Wayne Bollinger, Hai Hsia Chen, Sumit DasGupta, Edward P. Hsieh, Andrew D. Huber, Edward J. Hughes, Zahi M. Kurzum, Vasant B. Rao, Thepthai Tabtieng, Vigen Valijan, David Y. Yang
1995 A* conf
Delay Analysis of the Distributed RC Line.
DAC
Vasant B. Rao
1994 J jnl
A characterization of the smallest eigenvalue of a graph.
J. Graph Theory
Madhav P. Desai, Vasant B. Rao
1993 J jnl
An exact solution to the transistor sizing problem for CMOS circuits using convex optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang
1993 J jnl
Constructive Heuristics and Lower Bounds for Graph Partitioning Based on a Principal-Components Approximation.
SIAM J. Matrix Anal. Appl.
K. S. Arun, Vasant B. Rao
1993 J jnl
On the Convergence of Reversible Markov Chains.
SIAM J. Matrix Anal. Appl.
Madhav P. Desai, Vasant B. Rao
1991 A conf
A Convex Optimization Approach to Transistor Sizing for CMOS Circuits.
ICCAD
Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya
1991 J jnl
Combinatorial optimization by stochastic evolution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Youssef Saab, Vasant B. Rao
1991 J jnl
Consistency checking and optimization of macromodels.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yun-Cheng Ju, Vasant B. Rao, Resve A. Saleh
1991 Misc conf
Rank reduction in graph partitioning.
ICASSP
K. S. Arun, Vasant B. Rao
1990 J jnl
Fast effective heuristics for the graph bisectioning problem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Youssef Saab, Vasant B. Rao
1990 A* conf
Stochastic Evolution: a Fast Effective Heuristic for Some Generic Layout Problems.
DAC
Youssef Saab, Vasant B. Rao
1989 — conf
A Stochastic Algorithm for Circuit Bi-Partitioning.
Great Lakes Computer Science Conference
Youssef Saab, Vasant B. Rao
1989 A* conf
An Evolution-Based Approach to Partitioning ASIC Systems.
DAC
Youssef Saab, Vasant B. Rao
1988 — conf
Multi-Input Fuzzy Inference Engine on a Systolic Array.
IEA/AIE (Vol. 2)
MahmMahmoud A. Manzoul, Vasant B. Rao
1988 A conf
Partitioning issues in circuit simulation on multiprocessors.
ICCAD
David C. Yeh, Vasant B. Rao
1987 A* conf
HPEX: A Hierarchical Parasitic Circuit Extractor.
DAC
Shun-Lin Su, Vasant B. Rao, Timothy N. Trick
1987 J jnl
Network Partitioning and Ordering for MOS VLSI Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Vasant B. Rao, Timothy N. Trick
1985 — —
Switch-Level Timing Simulation of MOS VLSI Circuits
Vasant B. Rao