Varadan Savulimedu Veeravalli

15 papers B 1C 7Journal 3Unranked 4

Year	Rank	Type	Title / Venue / Authors
2017	—	`conf`	A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study. ATS Marko S. Andjelkovic, Milos Krstic, Rolf Kraemer, Varadan Savulimedu Veeravalli, Andreas Steininger
2017	J	`jnl`	A versatile architecture for long-term monitoring of single-event transient durations. Microprocess. Microsystems Varadan Savulimedu Veeravalli, Andreas Steininger, Ulrich Schmid
2017	C	`conf`	Setup for an Experimental Study of Radiation Effects in 65nm CMOS. DSD Bernhard Fritz, Andreas Steininger, Václav Simek, Varadan Savulimedu Veeravalli
2016	C	`conf`	Design and Physical Implementation of a Target ASIC for SET Experiments. DSD Varadan Savulimedu Veeravalli, Andreas Steininger
2016	B	`conf`	Study of a delayed single-event effect in the Muller C-element. ETS Varadan Savulimedu Veeravalli, Andreas Steininger
2015	J	`jnl`	Building reliable systems-on-chip in nanoscale technologies. Elektrotech. Informationstechnik Andreas Steininger, Horst Zimmermann, Axel Jantsch, Michael Hofbauer, Ulrich Schmid, Kurt Schweiger, Varadan Savulimedu Veeravalli
2015	C	`conf`	Reliable and Continuous Measurement of SET Pulse Widths. DSD Varadan Savulimedu Veeravalli, Andreas Steininger
2014	—	`conf`	Architecture for monitoring SET propagation in 16-bit Sklansky adder. ISQED Varadan Savulimedu Veeravalli, Andreas Steininger
2014	C	`conf`	Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. ICCD Andreas Steininger, Varadan Savulimedu Veeravalli, Dan Alexandrescu, Enrico Costenaro, Lorena Anghel
2014	—	`conf`	Measuring SET pulsewidths in logic gates using digital infrastructure. ISQED Varadan Savulimedu Veeravalli, Andreas Steininger, Ulrich Schmid
2013	J	`jnl`	An infrastructure for accurate characterization of single-event transients in digital circuits. Microprocess. Microsystems Varadan Savulimedu Veeravalli, Thomas Polzer, Ulrich Schmid, Andreas Steininger, Michael Hofbauer, Kurt Schweiger, Horst Dietrich, Kerstin Schneider-Hornstein, Horst Zimmermann, Kay-Obbe Voss, Bruno Merk, Michael Hajek
2013	—	`conf`	Modular Redundancy in a GALS System Using Asynchronous Recovery Links. ASYNC Jakob Lechner, Varadan Savulimedu Veeravalli
2012	C	`conf`	Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip. DSD Varadan Savulimedu Veeravalli, Thomas Polzer, Andreas Steininger, Ulrich Schmid
2012	C	`conf`	Protecting an Asynchronous NoC against Transient Channel Faults. DSD Syed Rameez Naqvi, Varadan Savulimedu Veeravalli, Andreas Steininger
2012	C	`conf`	Radiation-tolerant combinational gates - an implementation based comparison. DDECS Varadan Savulimedu Veeravalli, Andreas Steininger