Vanderlei Bonato

47 papers A 1B 3C 4Misc 1Journal 19Unranked 17
YearRankTypeTitle / Venue / Authors
2025 conf
BRACIS (1)
Eduardo Sperle Honorato, Vanderlei Bonato, Denis Fernando Wolf
2025 conf
ARC
Téo Sobrino Alves, Vanderlei Bonato
2025 J jnl
J. Braz. Comput. Soc.
Leandro de Souza Rosa, Christos-Savvas Bouganis, Vanderlei Bonato
2024 conf
IWOMP
Pedro Henrique Di Francia Rosso, Lucian Petrica, Nusrat Jahan Lisa, Márcio Machado Pereira, Sandro Rigo, Hervé Yviquel, Vanderlei Bonato, Emilio Francesquini, Guido Araujo
2024 J jnl
J. Signal Process. Syst.
André Bannwart Perina, Jürgen Becker, Vanderlei Bonato
2023 J jnl
J. Signal Process. Syst.
Caio C. S. Oliveira, Vanderlei Bonato
2022 J jnl
Appl. Soft Comput.
Guilherme A. Bileki, Flavio Barboza, Luiz Henrique Claudino Silva, Vanderlei Bonato
2021 J jnl
Appl. Soft Comput.
Vanderlei Bonato, Christos-Savvas Bouganis
2021 J jnl
IEEE Trans. Computers
André B. Perina, Arthur Silitonga, Jürgen Becker, Vanderlei Bonato
2021 J jnl
Microprocess. Microsystems
Leandro de Souza Rosa, Christos-Savvas Bouganis, Vanderlei Bonato
2019 conf
FPT
André Bannwart Perina, Jürgen Becker, Vanderlei Bonato
2019 conf
ICECS
André Bannwart Perina, Jürgen Becker, Vanderlei Bonato
2019 J jnl
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Leandro de Souza Rosa, Christos-Savvas Bouganis, Vanderlei Bonato
2018 J jnl
J. Signal Process. Syst.
Leandro de Souza Rosa, Aravind Dasu, Pedro C. Diniz, Vanderlei Bonato
2018 conf
FPT
André Bannwart Perina, Vanderlei Bonato
2018 conf
FPT
Leandro de Souza Rosa, Vanderlei Bonato, Christos-Savvas Bouganis
2017 C conf
DSD
André B. Perina, Paulo Matias, Eduardo Marques, Vanderlei Bonato, João Miguel Gago Pontes de Brito Lima
2017 J jnl
Microprocess. Microsystems
Christos-Savvas Bouganis, Marek Gorgon, Vanderlei Bonato
2016 ed.
ARC
Vanderlei Bonato, Christos Bouganis, Marek Gorgon
2016 J jnl
Appl. Soft Comput.
Leandro de Souza Rosa, Alexandre C. B. Delbem, Claudio Fabiano Motta Toledo, Vanderlei Bonato
2015 J jnl
IET Comput. Digit. Tech.
Bruno de Abreu Silva, Lucas Albers Cuminato, Alexandre C. B. Delbem, Pedro C. Diniz, Vanderlei Bonato
2015 C conf
DSD
Helio Fernandes da Cunha Junior, Bruno de Abreu Silva, Vanderlei Bonato
2015 conf
SBCCI
Bruno A. Silva, Lucas Albers Cuminato, Vanderlei Bonato, Pedro C. Diniz
2015 conf
ReConFig
Bruno A. Silva, Alexandre C. B. Delbem, Vanderlei Bonato, Pedro C. Diniz
2014 J jnl
Int. J. Nat. Comput. Res.
Marcilyanne Moreira Gois, Paulo Matias, André Bannwart Perina, Vanderlei Bonato, Alexandre C. B. Delbem
2014 J jnl
Int. J. Reconfigurable Comput.
Vanderlei Bonato, Marcio Merino Fernandes, João M. P. Cardoso, Eduardo Marques
2014 J jnl
CoRR
André Bannwart Perina, Marcilyanne Moreira Gois, Paulo Matias, João M. P. Cardoso, Alexandre C. B. Delbem, Vanderlei Bonato
2013 J jnl
J. Signal Process. Syst.
Vanderlei Bonato, Bruno F. Mazzotti, Marcio Merino Fernandes, Eduardo Marques
2013 J jnl
J. Braz. Comput. Soc.
Leandro de Souza Rosa, Vanderlei Bonato
2012 C conf
IECON
Sergio H. M. Durand, Vanderlei Bonato
2012 C conf
IECON
Roberto de Medeiros, Marcilyanne Moreira Gois, Vanderlei Bonato
2012 conf
SIES
Roberto de Medeiros, Miguel Góis, Drausio Linardi Rossi, Vanderlei Bonato
2012 B conf
FPL
Bruno de Abreu Silva, Vanderlei Bonato
2012 conf
ReConFig
Bruno de Abreu Silva, Lucas Albers Cuminato, Vanderlei Bonato
2011 conf
ReConFig
Drausio Linardi Rossi, Vanderlei Bonato, Eduardo Marques, João Miguel Gago Pontes de Brito Lima
2009 J jnl
J. Signal Process. Syst.
Vanderlei Bonato, Eduardo Marques, George A. Constantinides
2009 conf
SIES
Vanderlei Bonato, Eduardo Marques
2008 conf
ARC
Vanderlei Bonato, Eduardo Marques, George A. Constantinides
2008 J jnl
IEEE Trans. Circuits Syst. Video Technol.
Vanderlei Bonato, Eduardo Marques, George A. Constantinides
2008
Vanderlei Bonato
2007 B conf
FPL
Vanderlei Bonato, Eduardo Marques, George A. Constantinides
2007 conf
SIES
Vanderlei Bonato, Rafael Peron, Denis F. Wolf, José A. M. de Holanda, Eduardo Marques, João M. P. Cardoso
2006 conf
ARC
Vanderlei Bonato, José A. M. de Holanda, Eduardo Marques
2004 conf
ICINCO (2)
Vanderlei Bonato, Adriano K. Sanches, Marcio Merino Fernandes, João M. P. Cardoso, Eduardo do Valle Simões, Eduardo Marques
2004 Misc conf
WCAE
Vanderlei Bonato, Ricardo Menotti, Eduardo do Valle Simões, Marcio Merino Fernandes, Eduardo Marques
2003 A conf
FPGA
Vanderlei Bonato, Rolf Fredi Molz, João Carlos Furtado, Marcos Flôres Ferrão, Fernando Gehm Moraes
2003 B conf
FPL
Vanderlei Bonato, Rolf Fredi Molz, João Carlos Furtado, Marcos Flôres Ferrão, Fernando Gehm Moraes
redb/extractors/decompiler/bninja/arch/x86.py
← Index redb/extractors/decompiler/bninja/arch/x86.py python
from binaryninja.enums import (
    InstructionTextTokenType,
)

# Support both package and standalone imports
try:
    from .architecture import Architecture
except ImportError:
    # Fallback to absolute imports (for multiprocessing spawned processes)
    from redb.extractors.decompiler.bninja.arch.architecture import Architecture


class Arch_x86(Architecture):
    """The concrete class for architecture-dependent details for x86_64"""

    def __init__(self):
        # general purpose registers for 64bits
        self.gpr_64 = [
            "RAX",
            "RBX",
            "RCX",
            "RDX",
            "RSI",
            "RDIR9",
            "R10",
            "R11",
            "R12",
            "R13",
            "R14",
            "R15",
        ]

        self.gpr_32 = [
            "EAX",
            "EBX",
            "ECX",
            "EDX",
            "ESI",
            "EDI",
            "R8D",
            "R9D",
            "R10D",
            "R11D",
            "R12D",
            "R13D",
            "R14D",
            "R15D",
        ]

        self.gpr_16 = [
            "AX",
            "BX",
            "CX",
            "DX",
            "SI",
            "DI",
            "R8W",
            "R9W",
            "R10W",
            "R11W",
            "R12W",
            "R13W",
            "R14W",
            "R15W",
        ]

        self.gpr_8 = [
            "AL",
            "BL",
            "CL",
            "DL",
            "SIL",
            "DIL",
            "R8B",
            "R9B",
            "R10B",
            "R11B",
            "R12B",
            "R13B",
            "R14B",
            "R15B",
        ]

        self.fpu_x87 = ["ST0", "ST1", "ST2", "ST3", "ST4", "ST5", "ST6", "ST7"]

        self.sse_xmm = [
            "XMM0",
            "XMM1",
            "XMM2",
            "XMM3",
            "XMM4",
            "XMM5",
            "XMM6",
            "XMM7",
            "XMM8",
            "XMM9",
            "XMM10",
            "XMM11",
            "XMM12",
            "XMM13",
            "XMM14",
            "XMM15",
        ]

        self.avx_ymm = [
            "YMM0",
            "YMM1",
            "YMM2",
            "YMM3",
            "YMM4",
            "YMM5",
            "YMM6",
            "YMM7",
            "YMM8",
            "YMM9",
            "YMM10",
            "YMM11",
            "YMM12",
            "YMM13",
            "YMM14",
            "YMM15",
        ]
        self.flags = ["FLAGS", "EFLAGS", "RFLAGS"]
        self.stack_registers = ["RBP", "RSP", "SP", "BP"]
        self.size = 8
        self.global_registers = (
            self.gpr_64
            + self.gpr_32
            + self.gpr_16
            + self.gpr_8
            + self.fpu_x87
            + self.sse_xmm
            + self.avx_ymm
        )
        self.opcode_categories = self._initialize_opcode_categories()

        ## instructions
        self.instructions = []

    def is_register(self, register):
        register = register.upper()
        return register in self.global_registers

    def is_general_purpose_register(self, register):
        register = register.upper()
        return (
            register in self.gpr_64
            or register in self.gpr_32
            or register in self.gpr_16
            or register in self.gpr_8
        )

    def is_stack_register(self, register):
        register = register.upper()
        return register in self.stack_registers

    def is_xmm_register(self, register):
        register = register.upper()
        return register in self.sse_xmm

    def is_control_flow(self, instr_tokens):
        return False

    def is_control_flow_instruction(self, instr_tokens):
        """Check if an instruction is a control flow instruction (jump, call, return, loop)."""
        try:
            # Extract the mnemonic from the instruction tokens
            mnemonic = None
            for token in instr_tokens:
                if token.type == InstructionTextTokenType.InstructionToken:
                    mnemonic = token.text.upper()
                    break

            if not mnemonic:
                return False

            # Check if it's a jump, call, return, or loop instruction
            return (
                mnemonic.startswith("J")  # All jumps (JMP, JE, JNE, etc.)
                or mnemonic == "CALL"  # Function calls
                or mnemonic == "RET"  # Return
                or mnemonic == "RETN"  # Another form of return
                or mnemonic.startswith("LOOP")
            )  # Loop instructions

        except Exception as e:
            print(e)
            # If we can't determine, assume it's not a control flow instruction
            return False

    def is_control_flow_instruction_by_mnemonic(self, mnemonic):
        """Check if an instruction is a control flow instruction based on its mnemonic."""
        if not mnemonic:
            return False

        mnemonic = mnemonic.upper()
        return (
            mnemonic.startswith("J")  # All jumps (JMP, JE, JNE, etc.)
            or mnemonic == "CALL"  # Function calls
            or mnemonic == "RET"  # Return
            or mnemonic == "RETN"  # Another form of return
            or mnemonic.startswith("LOOP")
        )

    def _initialize_opcode_categories(self):
        """Initialize mapping of opcodes to categories similar to Ghidra's implementation."""
        opcode_categories = {}
        opcode_index = {}  # Add this to mimic Ghidra's opcodeIndex

        # Define common opcodes array similar to Ghidra's COMMON_OPCODES
        COMMON_OPCODES = [
            # Core instructions (tracked individually)
            "MOV",
            "PUSH",
            "POP",
            "LEA",
            "CALL",
            "RET",  # Data movement and control
            "ADD",
            "SUB",
            "MUL",
            "DIV",  # Basic arithmetic
            "AND",
            "OR",
            "XOR",
            "NOT",  # Logical operations
            "JMP",
            "JE",
            "JNE",  # Basic jumps
            "TEST",
            "CMP",  # Comparisons
            # Grouped categories (aggregated tracking)
            "SIMD_MOVE",  # MOVAPS, MOVDQA, MOVDQU, etc.
            "COND_JUMP_EXT",  # Other conditional jumps (JG, JL, JGE, etc.)
            "STRING_OP",  # MOVS, STOS, LODS, SCAS, CMPS
            "STACK_ADV",  # ENTER, LEAVE, PUSHA, POPA
            "ARITHMETIC_ADV",  # IMUL, IDIV, ADC, SBB
            "BIT_OP",  # SHL, SHR, SAR, ROL, ROR, etc.
            "FPU_OP",  # FLD, FST, FADD, etc.
            "SYSTEM_OP",  # SYSCALL, INT, SYSENTER
            "CRYPTO_OP",  # AES*, SHA* instructions
            "MISC_OP",  # Rare but interesting (CPUID, RDTSC, etc.)
        ]

        # Create index map like Ghidra
        for i, opcode in enumerate(COMMON_OPCODES):
            opcode_index[opcode] = i

        # Now categorize opcodes using if/elif/else structure like in Ghidra
        for opcode in COMMON_OPCODES:
            # String Operations (checking these first to avoid MOV confusion)
            if opcode.startswith("MOVS") or opcode in [
                "STOS",
                "LODS",
                "SCAS",
                "CMPS",
                "REP",
                "REPE",
                "REPNE",
            ]:
                opcode_categories[opcode] = "STRING_MANIPULATION"

            # Data Movement (after string ops to avoid MOVS confusion)
            elif opcode.startswith("MOV") or opcode in ["LEA", "XCHG"]:
                opcode_categories[opcode] = "DATA_MOVEMENT"

            # Stack Operations
            elif opcode in ["PUSH", "POP", "ENTER", "LEAVE", "PUSHA", "POPA"]:
                opcode_categories[opcode] = "STACK_MANAGEMENT"

            # Control Flow (non-conditional)
            elif opcode in ["JMP", "CALL", "RET"]:
                opcode_categories[opcode] = "CONTROL_FLOW"

            # Conditional Jumps and Loops
            elif opcode.startswith("J") or opcode.startswith("LOOP"):
                opcode_categories[opcode] = "CONDITIONAL_JUMP"

            # Arithmetic
            elif opcode in [
                "ADD",
                "SUB",
                "MUL",
                "DIV",
                "IMUL",
                "IDIV",
                "ADC",
                "SBB",
                "INC",
                "DEC",
                "NEG",
            ]:
                opcode_categories[opcode] = "ARITHMETIC"

            # Logical
            elif opcode in ["AND", "OR", "XOR", "NOT", "TEST", "CMP"]:
                opcode_categories[opcode] = "LOGICAL"

            # Shifts & Rotates
            elif opcode in ["SHL", "SHR", "SAR", "SAL", "ROL", "ROR", "RCL", "RCR"]:
                opcode_categories[opcode] = "SHIFT_ROTATE"

            # System & Interrupts
            elif opcode in [
                "SYSCALL",
                "INT",
                "SYSENTER",
                "SYSEXIT",
                "SGDT",
                "SIDT",
                "SLDT",
                "WRMSR",
                "RDMSR",
            ]:
                opcode_categories[opcode] = "SYSTEM_CALLS"

            # Floating Point
            elif opcode.startswith("F"):
                opcode_categories[opcode] = "FPU_ARITHMETIC"

            # System Information and Random Number Generation
            elif opcode in ["PUSHF", "POPF", "CPUID", "RDTSC", "RDRAND", "RDSEED"]:
                opcode_categories[opcode] = "CPU_FEATURES"

            # Cryptography
            elif opcode.startswith("AES") or opcode.startswith("SHA"):
                opcode_categories[opcode] = "CRYPTOGRAPHIC"

            # Miscellaneous (including flag operations)
            else:
                opcode_categories[opcode] = "MISC"

        # Additional categorization for opcodes not in COMMON_OPCODES
        # This can be used in the normalize_opcode method

        # Store both maps as instance variables
        # self.opcode_categories = opcode_categories
        self.opcode_index = opcode_index

        return opcode_categories

    def is_simd_register(self, register):
        return register in self.sse_xmm