Vanderlei Bonato

47 papers A 1B 3C 4Misc 1Journal 19Unranked 17

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Cost-Efficient Visual Perception for Autonomous Vehicles: Leveraging Attention-Based Sensor Fusion to Maintain Performance. BRACIS (1) Eduardo Sperle Honorato, Vanderlei Bonato, Denis Fernando Wolf
2025	—	`conf`	Dynamic Function Exchange in FPGA to Redefine RISC-V Multicore Architectures at Runtime. ARC Téo Sobrino Alves, Vanderlei Bonato
2025	J	`jnl`	Efficient Number of Functional Units and Loop Pipeline Design Space Exploration for High-Level Synthesis. J. Braz. Comput. Soc. Leandro de Souza Rosa, Christos-Savvas Bouganis, Vanderlei Bonato
2024	—	`conf`	Integrating Multi-FPGA Acceleration to OpenMP Distributed Computing. IWOMP Pedro Henrique Di Francia Rosso, Lucian Petrica, Nusrat Jahan Lisa, Márcio Machado Pereira, Sandro Rigo, Hervé Yviquel, Vanderlei Bonato, Emilio Francesquini, Guido Araujo
2024	J	`jnl`	Memory Aware Design Optimisation for High-Level Synthesis. J. Signal Process. Syst. André Bannwart Perina, Jürgen Becker, Vanderlei Bonato
2023	J	`jnl`	A FAST Hardware Decoder Optimized for Template Features to Obtain Order Book Data in Low Latency. J. Signal Process. Syst. Caio C. S. Oliveira, Vanderlei Bonato
2022	J	`jnl`	Order book mid-price movement inference by CatBoost classifier from convolutional feature maps. Appl. Soft Comput. Guilherme A. Bileki, Flavio Barboza, Luiz Henrique Claudino Silva, Vanderlei Bonato
2021	J	`jnl`	Class-specific early exit design methodology for convolutional neural networks. Appl. Soft Comput. Vanderlei Bonato, Christos-Savvas Bouganis
2021	J	`jnl`	Fast Resource and Timing Aware Design Optimisation for High-Level Synthesis. IEEE Trans. Computers André B. Perina, Arthur Silitonga, Jürgen Becker, Vanderlei Bonato
2021	J	`jnl`	Non-iterative SDC modulo scheduling for high-level synthesis. Microprocess. Microsystems Leandro de Souza Rosa, Christos-Savvas Bouganis, Vanderlei Bonato
2019	—	`conf`	Lina: Timing-Constrained High-Level Synthesis Performance Estimator for Fast DSE. FPT André Bannwart Perina, Jürgen Becker, Vanderlei Bonato
2019	—	`conf`	ProfCounter: Line-Level Cycle Counter for Xilinx OpenCL High-Level Synthesis. ICECS André Bannwart Perina, Jürgen Becker, Vanderlei Bonato
2019	J	`jnl`	Scaling Up Modulo Scheduling for High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Leandro de Souza Rosa, Christos-Savvas Bouganis, Vanderlei Bonato
2018	J	`jnl`	A Faddeev Systolic Array for EKF-SLAM and its Arithmetic Data Representation Impact on FPGA. J. Signal Process. Syst. Leandro de Souza Rosa, Aravind Dasu, Pedro C. Diniz, Vanderlei Bonato
2018	—	`conf`	Mapping Estimator for OpenCL Heterogeneous Accelerators. FPT André Bannwart Perina, Vanderlei Bonato
2018	—	`conf`	Scaling Up Loop Pipelining for High-Level Synthesis: A Non-iterative Approach. FPT Leandro de Souza Rosa, Vanderlei Bonato, Christos-Savvas Bouganis
2017	C	`conf`	Exploiting Kant and Kimura's Matrix Inversion Algorithm on FPGA. DSD André B. Perina, Paulo Matias, Eduardo Marques, Vanderlei Bonato, João Miguel Gago Pontes de Brito Lima
2017	J	`jnl`	Special issue on applied reconfigurable computing. Microprocess. Microsystems Christos-Savvas Bouganis, Marek Gorgon, Vanderlei Bonato
2016	—	`ed.`	Applied Reconfigurable Computing - 12th International Symposium, ARC 2016, Mangaratiba, RJ, Brazil, March 22-24, 2016, Proceedings ARC Vanderlei Bonato, Christos Bouganis, Marek Gorgon
2016	J	`jnl`	Design and analysis of evolutionary bit-length optimization algorithms for floating to fixed-point conversion. Appl. Soft Comput. Leandro de Souza Rosa, Alexandre C. B. Delbem, Claudio Fabiano Motta Toledo, Vanderlei Bonato
2015	J	`jnl`	Application-oriented cache memory configuration for energy efficiency in multi-cores. IET Comput. Digit. Tech. Bruno de Abreu Silva, Lucas Albers Cuminato, Alexandre C. B. Delbem, Pedro C. Diniz, Vanderlei Bonato
2015	C	`conf`	Parameterizable Ethernet Network-on-Chip Architecture on FPGA. DSD Helio Fernandes da Cunha Junior, Bruno de Abreu Silva, Vanderlei Bonato
2015	—	`conf`	Run-time Cache Configuration for the LEON-3 Embedded Processor. SBCCI Bruno A. Silva, Lucas Albers Cuminato, Vanderlei Bonato, Pedro C. Diniz
2015	—	`conf`	Runtime mapping and scheduling for energy efficiency in heterogeneous multi-core systems. ReConFig Bruno A. Silva, Alexandre C. B. Delbem, Vanderlei Bonato, Pedro C. Diniz
2014	J	`jnl`	A Parallel Hardware Architecture based on Node-Depth Encoding to Solve Network Design Problems. Int. J. Nat. Comput. Res. Marcilyanne Moreira Gois, Paulo Matias, André Bannwart Perina, Vanderlei Bonato, Alexandre C. B. Delbem
2014	J	`jnl`	Practical Education Fostered by Research Projects in an Embedded Systems Course. Int. J. Reconfigurable Comput. Vanderlei Bonato, Marcio Merino Fernandes, João M. P. Cardoso, Eduardo Marques
2014	J	`jnl`	Representation of Evolutionary Algorithms in FPGA Cluster for Project of Large-Scale Networks. CoRR André Bannwart Perina, Marcilyanne Moreira Gois, Paulo Matias, João M. P. Cardoso, Alexandre C. B. Delbem, Vanderlei Bonato
2013	J	`jnl`	A Mersenne Twister Hardware Implementation for the Monte Carlo Localization Algorithm. J. Signal Process. Syst. Vanderlei Bonato, Bruno F. Mazzotti, Marcio Merino Fernandes, Eduardo Marques
2013	J	`jnl`	A method to convert floating to fixed-point EKF-SLAM for embedded robotics. J. Braz. Comput. Soc. Leandro de Souza Rosa, Vanderlei Bonato
2012	C	`conf`	A tool to support Bluespec SystemVerilog coding based on UML diagrams. IECON Sergio H. M. Durand, Vanderlei Bonato
2012	C	`conf`	Designing FPGA-based embedded systems with MARTE: A PIM to PSM converter. IECON Roberto de Medeiros, Marcilyanne Moreira Gois, Vanderlei Bonato
2012	—	`conf`	Designing embedded systems with MARTE: A PIM to PSM converter. SIES Roberto de Medeiros, Miguel Góis, Drausio Linardi Rossi, Vanderlei Bonato
2012	B	`conf`	Power/performance optimization in FPGA-based asymmetric multi-core systems. FPL Bruno de Abreu Silva, Vanderlei Bonato
2012	—	`conf`	Reducing the overall cache miss rate using different cache sizes for Heterogeneous Multi-core Processors. ReConFig Bruno de Abreu Silva, Lucas Albers Cuminato, Vanderlei Bonato
2011	—	`conf`	A PID Controller Applied to the Gain Control of a CMOS Camera Using Reconfigurable Computing. ReConFig Drausio Linardi Rossi, Vanderlei Bonato, Eduardo Marques, João Miguel Gago Pontes de Brito Lima
2009	J	`jnl`	A Floating-point Extended Kalman Filter Implementation for Autonomous Mobile Robots. J. Signal Process. Syst. Vanderlei Bonato, Eduardo Marques, George A. Constantinides
2009	—	`conf`	RoboArch: A component-based tool proposal for developing hardware architecture for mobile robots. SIES Vanderlei Bonato, Eduardo Marques
2008	—	`conf`	A Parallel Hardware Architecture for Image Feature Detection. ARC Vanderlei Bonato, Eduardo Marques, George A. Constantinides
2008	J	`jnl`	A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection. IEEE Trans. Circuits Syst. Video Technol. Vanderlei Bonato, Eduardo Marques, George A. Constantinides
2008	—	`—`	Proposal of an FPGA hardware architecture for SLAM using multi-cameras and applied to mobile robotics (Proposta de uma arquitetura de hardware em FPGA implementada para SLAM com multi-câmeras aplicada à robótica móvel). Vanderlei Bonato
2007	B	`conf`	A floating-point Extended Kalman Filter implementation for autonomous mobile robots. FPL Vanderlei Bonato, Eduardo Marques, George A. Constantinides
2007	—	`conf`	An FPGA Implementation for a Kalman Filter with Application to Mobile Robotics. SIES Vanderlei Bonato, Rafael Peron, Denis F. Wolf, José A. M. de Holanda, Eduardo Marques, João M. P. Cardoso
2006	—	`conf`	An Embedded Multi-camera System for Simultaneous Localization and Mapping. ARC Vanderlei Bonato, José A. M. de Holanda, Eduardo Marques
2004	—	`conf`	A Real Time Gesture Recognition System for Mobile Robots. ICINCO (2) Vanderlei Bonato, Adriano K. Sanches, Marcio Merino Fernandes, João M. P. Cardoso, Eduardo do Valle Simões, Eduardo Marques
2004	Misc	`conf`	Teaching embedded systems with FPGAs throughout a computer science course. WCAE Vanderlei Bonato, Ricardo Menotti, Eduardo do Valle Simões, Marcio Merino Fernandes, Eduardo Marques
2003	A	`conf`	Design of a fingerprint system using a hardware/software environment. FPGA Vanderlei Bonato, Rolf Fredi Molz, João Carlos Furtado, Marcos Flôres Ferrão, Fernando Gehm Moraes
2003	B	`conf`	Propose of a Hardware Implementation for Fingerprint Systems. FPL Vanderlei Bonato, Rolf Fredi Molz, João Carlos Furtado, Marcos Flôres Ferrão, Fernando Gehm Moraes