Valery Sklyarov

70 papers A 1B 10C 13Misc 6Journal 14Unranked 25

Year	Rank	Type	Title / Venue / Authors
2019	—	`book`	FPGA-BASED Hardware Accelerators Iouliia Skliarova, Valery Sklyarov
2017	J	`jnl`	Data processing in the firmware systems for logic control based on search networks. Autom. Remote. Control. Valery Sklyarov, Iouliia Skliarova
2017	—	`conf`	RAM-based mergers for data sort and frequent item computation. MIPRO Artjem Rjabov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson
2017	C	`conf`	Reconfigurable systems in engineering education: Best practices and future trends. EDUCON Iouliia Skliarova, Valery Sklyarov, Alexander Sudnitson, Margus Kruus
2016	J	`jnl`	Computing Sorted Subsets for Data Processing in Communicating Software/Hardware Control Systems. Int. J. Comput. Commun. Control Valery Sklyarov, Iouliia Skliarova, Artjem Rjabov, Alexander Sudnitson
2016	J	`jnl`	On-Chip Reconfigurable Hardware Accelerators for Popcount Computations. Int. J. Reconfigurable Comput. Valery Sklyarov, Iouliia Skliarova, João Paulo Sá da Silva
2015	C	`conf`	Analysis and Comparison of Attainable Hardware Acceleration in All Programmable Systems-on-Chip. DSD Valery Sklyarov, Iouliia Skliarova, João Paulo Sá da Silva, Alexander Sudnitson
2015	J	`jnl`	Comparison of On-chip Communications in Zynq-7000 All Programmable Systems-on-Chip. IEEE Embed. Syst. Lett. João Paulo Sá da Silva, Valery Sklyarov, Iouliia Skliarova
2015	J	`jnl`	Design and implementation of counting networks. Computing Valery Sklyarov, Iouliia Skliarova
2015	—	`conf`	FPGA-based time and cost effective Hamming weight comparators for binary vectors. EUROCON Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, Margus Kruus
2015	—	`conf`	Integration of high-level synthesis to the courses on reconfigurable digital systems. MIPRO Iouliia Skliarova, Valery Sklyarov, Alexander Sudnitson, Margus Kruus
2015	J	`jnl`	Multi-core DSP-based Vector Set Bits Counters/Comparators. J. Signal Process. Syst. Valery Sklyarov, Iouliia Skliarova
2014	—	`conf`	Design space exploration in multi-level computing systems. CompSysTech Valery Sklyarov, Iouliia Skliarova, João Paulo Sá da Silva, Alexander Sudnitson
2014	J	`jnl`	FPGA-based Accelerators for Parallel Data Sort. Appl. Comput. Syst. Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson
2014	J	`jnl`	High-performance implementation of regular and easily scalable sorting networks on an FPGA. Microprocess. Microsystems Valery Sklyarov, Iouliia Skliarova
2014	C	`conf`	Teaching FPGA-based systems. EDUCON Iouliia Skliarova, Valery Sklyarov, Alexander Sudnitson, Margus Kruus
2013	—	`conf`	Address-based data processing over N-ary trees. EUROCON Valery Sklyarov, Iouliia Skliarova, Margus Kruus, Dmitri Mihhailov, Alexander Sudnitson
2013	J	`jnl`	Hardware implementations of software programs based on hierarchical finite state machine models. Comput. Electr. Eng. Valery Sklyarov, Iouliia Skliarova
2013	—	`conf`	Implementation of address-based data sorting on different FPGA platforms. EWDTS Dmitri Mihhailov, Alexander Sudnitson, Valery Sklyarov, Iouliia Skliarova
2013	—	`conf`	Implementation of parallel operations over streams in extensible processing platforms. MWSCAS Valery Sklyarov, Iouliia Skliarova, Artjem Rjabov, Alexander Sudnitson
2013	—	`conf`	Optimization of address-based data sorting unit with external memory support. CompSysTech Dmitri Mihhailov, Artjem Rjabov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson
2012	C	`conf`	Methodology and international collaboration in teaching reconfigurable systems. EDUCON Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson
2012	—	`conf`	Performance evaluation for FPGA-based processing of tree-like structures. ICECS Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson
2011	C	`conf`	High-performance hardware accelerators for sorting and managing priorities. DDECS Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson
2011	B	`conf`	Implementation in FPGA of Address-Based Data Sorting. FPL Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson
2011	—	`conf`	Recursion and hierarchy in digital design and prototyping: a case study. CompSysTech Dmitri Mihhailov, Margus Kruus, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson
2010	—	`conf`	Application-specific hardware accelerator for implementing recursive sorting algorithms. FPT Dmitri Mihhailov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson
2010	—	`conf`	Parallel FPGA-Based Implementation of Recursive Sorting Algorithms. ReConFig Dmitri Mihhailov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson
2010	—	`conf`	Synthesis and Implementation of Hierarchical Finite State Machines with Implicit Modules. ReConFig Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson
2009	B	`conf`	Recursion in reconfigurable computing: A survey of implementation approaches. FPL Iouliia Skliarova, Valery Sklyarov
2008	Misc	`conf`	Multimedia Tools and Architectures for Hardware/Software Co-Simulation of Reconfigurable Systems. VLSI Design Valery Sklyarov, Iouliia Skliarova, Bruno Figueiredo Pimentel, Manuel Almeida
2008	Misc	`conf`	Recursive versus Iterative Algorithms for Solving Combinatorial Search Problems in Hardware. VLSI Design Iouliia Skliarova, Valery Sklyarov
2007	B	`conf`	A prototyping system for mobile devices. IWCMC Valery Sklyarov, Iouliia Skliarova, Manuel Almeida, Bruno Figueiredo Pimentel
2007	C	`conf`	Encoding Algorithms for Logic Synthesis. AICCSA Valery Sklyarov, Iouliia Skliarova
2007	Misc	`conf`	Reuse Technique in Hardware Design. IRI Valery Sklyarov, Iouliia Skliarova
2007	C	`conf`	Software/Configware Implementation of Combinatorial Algorithms. AICCSA Iouliia Skliarova, Valery Sklyarov
2006	—	`conf`	E-learning Tools and Web-resources for Teaching Reconfigurable Systems. Education for the 21st Century Valery Sklyarov, Iouliia Skliarova
2006	—	`conf`	Evolutionary Algorithm for State Encoding. IFIP AI Valery Sklyarov, Iouliia Skliarova
2006	C	`conf`	Multimedia Tools for Teaching Reconfigurable Systems. MoMM Valery Sklyarov, Iouliia Skliarova
2006	C	`conf`	Reconfigurable Systems and their Influence on Mobile and Multimedia Applications. MoMM Valery Sklyarov, Iouliia Skliarova
2006	—	`conf`	Recursive and Iterative Algorithms for N-ary Search Problems. IFIP PPAI Valery Sklyarov, Iouliia Skliarova
2005	C	`conf`	ARPA - A Technology Independent and Synthetizable System-on-Chip Model for Real-Time Applications. DSD Arnaldo S. R. Oliveira, Valery Sklyarov, António de Brito Ferrari
2005	B	`conf`	FPGA-based implementation and comparison of recursive and iterative algorithms. FPL Valery Sklyarov, Iouliia Skliarova, Bruno Figueiredo Pimentel
2005	J	`jnl`	Teaching reconfigurable systems: methods, tools, tutorials, and projects. IEEE Trans. Educ. Valery Sklyarov, Iouliia Skliarova
2004	J	`jnl`	FPGA-based implementation of recursive algorithms. Microprocess. Microsystems Valery Sklyarov
2004	B	`conf`	Hardware/Software Implementation of FPGA-Targeted Matrix-Oriented SAT Solvers. FPL Valery Sklyarov, Iouliia Skliarova, Bruno Figueiredo Pimentel, Joel Arrais
2003	C	`conf`	A Dynamically Reconfigurable Accelerator for Operations over Boolean and Ternary Vectors. DSD Valery Sklyarov, Iouliia Skliarova, Arnaldo S. R. Oliveira, António de Brito Ferrari
2003	—	`conf`	Architecture of a Reconfigurable Processor for Implementing Search Algorithm over Discrete Matrices. Engineering of Reconfigurable Systems and Algorithms Valery Sklyarov, Iouliia Skliarova
2003	C	`conf`	Design Tools and Reusable Libraries for FPGA-Based Digital Circuits. DSD Valery Sklyarov, Iouliia Skliarova, Pedro Almeida, Manuel Almeida
2003	—	`conf`	Design of Digital Circuits on the Basis of Hardware Templates. Embedded Systems and Applications Valery Sklyarov, Iouliia Skliarova
2003	B	`conf`	High-Level Design Tools for FPGA-Based Combinatorial Accelerators. FPL Valery Sklyarov, Iouliia Skliarova, Pedro Almeida, Manuel Almeida
2003	B	`conf`	Reconfigurable Systems in Education. FPL Valery Sklyarov, Iouliia Skliarova
2002	C	`conf`	An Evolutionary Algorithm for the Synthesis of RAM-Based FSMs. IEA/AIE Valery Sklyarov
2002	J	`jnl`	Hardware/software modeling of FPGA-based systems. Parallel Algorithms Appl. Valery Sklyarov
2002	J	`jnl`	Reconfigurable models of finite state machines and their implementation in FPGAs. J. Syst. Archit. Valery Sklyarov
2000	B	`conf`	Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs. FPL Valery Sklyarov
2000	—	`conf`	Synthesis of Control Circuits with Dynamically Modifiable Behavior on the Basis of Statically Reconfigurable FPGAs. SBCCI Valery Sklyarov
2000	Misc	`conf`	The Specification and Design of Parallel Logical Control Devices. PDPTA Arkadij Zakrevskij, Valery Sklyarov
1999	Misc	`conf`	Development System for FPGA-Based Digital Circuits. FCCM Valery Sklyarov, José A. Fonseca, Ricardo Sal Monteiro, Arnaldo S. R. Oliveira, Andreia Melo, Nuno Lau, Iouliia Skliarova, Paulo A. C. S. Neves, António de Brito Ferrari
1999	—	`conf`	Dynamically Reconfigurable Implementation of Control Circuits. VLSI Nuno Lau, Valery Sklyarov
1999	A	`conf`	FPGA-Targeted Development System for Embedded Applications. FPGA Valery Sklyarov, José A. Fonseca, Ricardo Sal Monteiro, Arnaldo S. R. Oliveira, Andreia Melo, Nuno Lau, Konstantin Kondratjuk, Iouliia Skliarova, Paulo A. C. S. Neves, António de Brito Ferrari
1999	Misc	`conf`	Graphical Description and Hardware Implementation of Parallel Control Algorithms. PDPTA Valery Sklyarov
1999	J	`jnl`	Hierarchical finite-state machines and their use for digital control. IEEE Trans. Very Large Scale Integr. Syst. Valery Sklyarov
1999	—	`conf`	Implementation of virtual control circuits in dynamically reconfigurable FPGAs. ICECS Arnaldo S. R. Oliveira, Valery Sklyarov
1999	B	`conf`	Specification, Implementation and Testing of HFSMs in Dynamically Reconfigurable FPGAs. FPL Arnaldo S. R. Oliveira, Andreia Melo, Valery Sklyarov
1998	—	`conf`	Design and implementation of control circuits based on dynamically reconfigurable FPGA. ICECS Valery Sklyarov, António de Brito Ferrari
1998	—	`conf`	Design of Virtual Digital Controllers Based on Dynamically Reconfigurable FPGAs. EUROMICRO Valery Sklyarov, Nuno Lau, Ricardo Sal Monteiro, Andreia Melo, Arnaldo S. R. Oliveira, Konstantin Kondratjuk
1998	B	`conf`	Integrated Development Environment for Logic Synthesis Based on Dynamically Reconfigurable FPGAs. FPL Valery Sklyarov, Ricardo Sal Monteiro, Nuno Lau, Andreia Melo, Arnaldo S. R. Oliveira, Konstantin Kondratjuk
1998	—	`conf`	Logic Synthesis of Reconfigurable Control Circuits based on Mutually Exclusive Reprogrammable Elements. SBCCI Valery Sklyarov
1998	—	`conf`	Synthesis Tools and Design Environment for Dynamically Reconfigurable FPGAs. SBCCI Valery Sklyarov, Nuno Lau, Arnaldo S. R. Oliveira, Andreia Melo, Konstantin Kondratjuk, António de Brito Ferrari, Ricardo Sal Monteiro, Iouliia Skliarova